Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752208AbdLMJEe (ORCPT ); Wed, 13 Dec 2017 04:04:34 -0500 Received: from mail-vk0-f45.google.com ([209.85.213.45]:38404 "EHLO mail-vk0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750795AbdLMJEP (ORCPT ); Wed, 13 Dec 2017 04:04:15 -0500 X-Google-Smtp-Source: ACJfBoucBe5JInVhk05ZMRuSbmtArLo9FNEw6CfuymUGl74QciJqJbFdnui76lLMlQBZ6i7HOAQLtMReRSy4PKZMjs0= MIME-Version: 1.0 In-Reply-To: <20171213085334.GA21382@gary-OptiPlex-3050> References: <9d0e976c3e60bf6834dffb6ef798ad2a03e1c9ac.1512723245.git.green.hu@gmail.com> <20171213021619.GA6254@gary-OptiPlex-3050> <20171213081949.GA18840@gary-OptiPlex-3050> <20171213085334.GA21382@gary-OptiPlex-3050> From: Greentime Hu Date: Wed, 13 Dec 2017 17:03:33 +0800 Message-ID: Subject: Re: [PATCH v3 09/33] nds32: Cache and TLB routines To: Guo Ren Cc: Greentime , Linux Kernel Mailing List , Arnd Bergmann , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , netdev , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial@vger.kernel.org, Geert Uytterhoeven , Linus Walleij , Mark Rutland , Greg KH , Vincent Chen Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1694 Lines: 50 2017-12-13 16:53 GMT+08:00 Guo Ren : > On Wed, Dec 13, 2017 at 04:30:41PM +0800, Greentime Hu wrote: >> 2017-12-13 16:19 GMT+08:00 Guo Ren : >> > On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote: >> > >> >> I think it should be fine if an interruption between mtsr_dsb and >> >> tlbop_rwr because this is a optimization by sw. >> > >> > Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will >> > break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the >> > vaddr, it will get wrong data unless the entry has been replaced out. >> >> Hi, Guo Ren: >> >> Thanks. I get your point. >> It is needed to be protected. >> I will fix it in the next version patch. >> >> if (vma->vm_mm == current->active_mm) { >> local_irq_save(flags); >> __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN); >> __nds32__tlbop_rwr(*pte); >> __nds32__isb(); >> local_irq_restore(flags); >> } > > If hardware tlbop_rwr could invalid NDS32_SR_TLB_VPN, then you needn't > protect. > I mean: > mtsr addr1 NDS32_SR_TLB_VPN > mtsr addr2 NDS32_SR_TLB_VPN > tlbop_rwr(*pte) // OK, and it will hit a hardware invalid bit internal. > tlbop_rwr(*pte) // SR_TLB_VPN invalided, then it will not cause problem. > > :) How my idea? Hi, Guo Ren: The reason I think it might have problem is that mtsr addr1 NDS32_SR_TLB_VPN interrupt coming mtsr addr2 NDS32_SR_TLB_VPN <- TLB_VPN has been set to addr2 tlbop_rwr(*pte); interrupt finish tlbop_rwr(*pte); <- it will use the wrong TLB_VPN I think all these TLB operations should be protected because tlbop will operate with TLB_VPN. Thanks :)