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From: Greentime Hu <green.hu@gmail.com>
Date: Wed, 13 Dec 2017 18:04:44 +0800
Message-ID: <CAEbi=3eo9WqpzaVK_KoGE3JnvwjYGG8bOnbCQTd5RpvrQ_ySTA@mail.gmail.com>
Subject: Re: [PATCH v3 09/33] nds32: Cache and TLB routines
To: Guo Ren <ren_guo@c-sky.com>
Cc: Greentime <greentime@andestech.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Arnd Bergmann <arnd@arndb.de>, linux-arch <linux-arch@vger.kernel.org>,
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        Linus Walleij <linus.walleij@linaro.org>,
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2017-12-13 17:45 GMT+08:00 Guo Ren <ren_guo@c-sky.com>:
> Hello,
>
> CPU team could improve the tlbop_*. Eg: Design a hardware
> internal flag bit for SR_TLB_VPN, tlbop_* will invalid it and mtsr
> SR_TLB_VPN will valid it.
>
> So:
> On Wed, Dec 13, 2017 at 05:03:33PM +0800, Greentime Hu wrote:
>> mtsr addr1 NDS32_SR_TLB_VPN
>>     interrupt coming
>>         mtsr addr2 NDS32_SR_TLB_VPN <- TLB_VPN has been set to addr2
>         mtsr SR_TLB_VPN will valid the flag bit
>>         tlbop_rwr(*pte);
>         tlbop_rwr will invalid SR_TLB_VPN flag bit
>>     interrupt finish
>> tlbop_rwr(*pte); <- it will use the wrong TLB_VPN
> Because SR_TLB_VPN is in a invalid state, no operation happen on
> tlbop_rwr.
>
> Then they are atomic safe ,no spin_lock_irq need.
> :)
>

Oh, I see. I may propose this idea to our ARCH colleagues for the next
version design.
Many thanks.