Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753223AbdLMOnX (ORCPT ); Wed, 13 Dec 2017 09:43:23 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:38168 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752995AbdLMOnU (ORCPT ); Wed, 13 Dec 2017 09:43:20 -0500 X-Google-Smtp-Source: ACJfBov0PwIAhGrM7yK/BP2FvSx4uWRUoH4+avoTieSvlO2UX68XkGK07IM6zTeDJHemPrsMKRh53Q== Date: Wed, 13 Dec 2017 22:43:09 +0800 From: hao_zhang To: thierry.reding@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, wens@csie.org, linus.walleij@linaro.org, maxime.ripard@free-electrons.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, linux-amlogic@lists.infradead.org, hao5781286@gmail.com Subject: [PATCH v4 1/4] dt-bindings: pwm: binding allwinner sun8i R40/V40/T3. Message-ID: <20171213144309.GA18167@arx-s1> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1099 Lines: 34 This patch adds allwinner R40, V40, T3 pwm binding documents. Signed-off-by: hao_zhang --- Documentation/devicetree/bindings/pwm/pwm-sun8i.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt new file mode 100644 index 0000000..76750d8 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i.txt @@ -0,0 +1,18 @@ +Allwinner sun8i R40/V40/T3 SoC PWM controller + +Required properties: +- compatible: should be one of: +- "allwinner,sun8i-r40-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: should be 3. See pwm.txt in this directory for a description of +the cells format. +- clocks: From common clock binding, handle to the parent clock. + +Example: + +pwm: pwm@1c23400 { + compatible = "allwinner,sun8i-r40-pwm"; + reg = <0x01c23400 0x154>; + clocks = <&osc24M>; + #pwm-cells = <3>; +}; -- 2.7.4