Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751829AbdLNLKO (ORCPT ); Thu, 14 Dec 2017 06:10:14 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:33707 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751589AbdLNLKL (ORCPT ); Thu, 14 Dec 2017 06:10:11 -0500 X-Google-Smtp-Source: ACJfBouTLDeBK8qC1/o7JQ4nEwLszswzL38xwQKpCAKtxU2ERfxkaNRwkqzoBNYH25tZuh12okgpAw== Subject: Re: [PATCH 1/3] dt-bindings: ARM: Mediatek: Fix ethsys documentation To: Stephen Boyd , Michael Turquette , linux@armlinux.org.uk Cc: sboyd@codeaurora.org, sean.wang@mediatek.com, chen.zhong@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org References: <20171201120708.30129-1-matthias.bgg@gmail.com> From: Matthias Brugger Message-ID: Date: Thu, 14 Dec 2017 12:10:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20171201120708.30129-1-matthias.bgg@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1019 Lines: 28 Hi Stephen, Michael, On 12/01/2017 01:07 PM, Matthias Brugger wrote: > The ethsys registers a reset controller, so we need to specify a > reset cell. This patch fixes the documentation. > > Signed-off-by: Matthias Brugger > --- > Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > index 7aa3fa167668..6cc7840ff37a 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt > @@ -20,4 +20,5 @@ ethsys: clock-controller@1b000000 { > compatible = "mediatek,mt2701-ethsys", "syscon"; > reg = <0 0x1b000000 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > Will you take this patch through the clk tree, or shall I take it through my SoC tree? Regards, Matthias