Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756741AbdLOXKj (ORCPT ); Fri, 15 Dec 2017 18:10:39 -0500 Received: from mail-oi0-f66.google.com ([209.85.218.66]:42559 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755848AbdLOXKg (ORCPT ); Fri, 15 Dec 2017 18:10:36 -0500 X-Google-Smtp-Source: ACJfBou65NRwzgL1ha0x2nsdnkrtFF4LGt82zXulmLEmtuec4V9jGhwxS9Ptl20lpvlKDfpqWo84Lw== Date: Fri, 15 Dec 2017 17:10:34 -0600 From: Rob Herring To: Abhishek Sahu Cc: Stephen Boyd , Michael Turquette , Andy Gross , David Brown , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 10/11] dt-bindings: clock: qcom: add misc resets for PCIE and NSS Message-ID: <20171215231034.wf6fhpbu7eqbjfp4@rob-hp-laptop> References: <1513175142-3702-1-git-send-email-absahu@codeaurora.org> <1513175142-3702-11-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1513175142-3702-11-git-send-email-absahu@codeaurora.org> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 435 Lines: 11 On Wed, Dec 13, 2017 at 07:55:41PM +0530, Abhishek Sahu wrote: > PCIE and NSS has MISC reset register in which single register has > multiple reset bit. The patch adds the DT bindings for these MISC > resets. > > Signed-off-by: Abhishek Sahu > --- > include/dt-bindings/clock/qcom,gcc-ipq8074.h | 42 ++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) Reviewed-by: Rob Herring