Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757015AbdLPQ1E (ORCPT ); Sat, 16 Dec 2017 11:27:04 -0500 Received: from mga18.intel.com ([134.134.136.126]:7684 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756959AbdLPQ05 (ORCPT ); Sat, 16 Dec 2017 11:26:57 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,411,1508828400"; d="scan'208";a="16569913" From: Jarkko Sakkinen To: intel-sgx-kernel-dev@lists.01.org, platform-driver-x86@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Haim Cohen , Jarkko Sakkinen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Len Brown , Kyle Huey , Borislav Petkov , Tom Lendacky , Greg Kroah-Hartman , Grzegorz Andrejczuk Subject: [PATCH v9 3/7] x86: add SGX definitions to msr-index.h Date: Sat, 16 Dec 2017 18:19:50 +0200 Message-Id: <20171216162200.20243-4-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171216162200.20243-1-jarkko.sakkinen@linux.intel.com> References: <20171216162200.20243-1-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1897 Lines: 48 From: Sean Christopherson ENCLS and ENCLU are usable if and only if SGX_ENABLE is set and After SGX is activated the IA32_SGXLEPUBKEYHASHn MSRs are writable if SGX_LC_WR is set and the feature control is locked. SGX related bits in IA32_FEATURE_CONTROL cannot be set before SGX is activated by the pre-boot firmware. SGX activation is triggered by setting bit 0 in the MSR 0x7a. Until SGX is activated, the LE hash MSRs are writable to allow pre-boot firmware to lock down the LE root key with a non-Intel value. Signed-off-by: Sean Christopherson Signed-off-by: Haim Cohen Signed-off-by: Jarkko Sakkinen Tested-by: Serge Ayoun --- arch/x86/include/asm/msr-index.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 34c4922bbc3f..8647a2470487 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -439,6 +439,8 @@ #define FEATURE_CONTROL_LOCKED (1<<0) #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) +#define FEATURE_CONTROL_SGX_ENABLE (1<<18) +#define FEATURE_CONTROL_SGX_LE_WR (1<<17) #define FEATURE_CONTROL_LMCE (1<<20) #define MSR_IA32_APICBASE 0x0000001b @@ -505,6 +507,12 @@ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +/* Intel SGX MSRs */ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F + /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) #define THERM_SHIFT_THRESHOLD0 8 -- 2.14.1