Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933502AbdLRJZt (ORCPT ); Mon, 18 Dec 2017 04:25:49 -0500 Received: from 6.mo68.mail-out.ovh.net ([46.105.63.100]:54958 "EHLO 6.mo68.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933488AbdLRJZq (ORCPT ); Mon, 18 Dec 2017 04:25:46 -0500 Subject: Re: [PATCH v2 03/19] ARM: dts: aspeed: Add LPC and child devices To: Joel Stanley , Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org References: <20171215062443.23059-1-joel@jms.id.au> <20171215062443.23059-4-joel@jms.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Mon, 18 Dec 2017 10:25:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20171215062443.23059-4-joel@jms.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-Ovh-Tracer-Id: 9914956056230792045 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtuddrgedtgddtgecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3329 Lines: 124 On 12/15/2017 07:24 AM, Joel Stanley wrote: > From: Andrew Jeffery > > Ensure the ordering is correct and add all of the children in the SoC > device trees for the ast2400 and ast2500. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Joel Stanley > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++---------- > 2 files changed, 52 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 100d092e6c07..a3bc5da7d42c 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -226,6 +226,41 @@ > status = "disabled"; > }; > > + lpc: lpc@1e789000 { > + compatible = "aspeed,ast2400-lpc", "simple-mfd"; > + reg = <0x1e789000 0x1000>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x1e789000 0x1000>; > + > + lpc_bmc: lpc-bmc@0 { > + compatible = "aspeed,ast2400-lpc-bmc"; > + reg = <0x0 0x80>; > + }; > + > + lpc_host: lpc-host@80 { > + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; > + reg = <0x80 0x1e0>; > + reg-io-width = <4>; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x80 0x1e0>; > + > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2400-lpc-ctrl"; > + reg = <0x0 0x80>; > + status = "disabled"; > + }; > + > + lhc: lhc@20 { > + compatible = "aspeed,ast2500-lhc"; aspeed,ast2400-lhc The layout of the registers are the same but there a couple of differences in the bit definitions between the two SoCs. a part from that : Reviewed-by: Cédric Le Goater C. > + reg = <0x20 0x24 0x48 0x8>; > + }; > + }; > + }; > + > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 1f9d28313f82..7861631940fe 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -266,6 +266,16 @@ > status = "disabled"; > }; > > + vuart: serial@1e787000 { > + compatible = "aspeed,ast2500-vuart"; > + reg = <0x1e787000 0x40>; > + reg-shift = <2>; > + interrupts = <10>; > + clocks = <&clk_uart>; > + no-loopback-test; > + status = "disabled"; > + }; > + > lpc: lpc@1e789000 { > compatible = "aspeed,ast2500-lpc", "simple-mfd"; > reg = <0x1e789000 0x1000>; > @@ -289,6 +299,13 @@ > > reg-io-width = <4>; > > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2500-lpc-ctrl"; > + reg = <0x0 0x80>; > + status = "disabled"; > + }; > + > + > lhc: lhc@20 { > compatible = "aspeed,ast2500-lhc"; > reg = <0x20 0x24 0x48 0x8>; > @@ -296,16 +313,6 @@ > }; > }; > > - vuart: serial@1e787000 { > - compatible = "aspeed,ast2500-vuart"; > - reg = <0x1e787000 0x40>; > - reg-shift = <2>; > - interrupts = <10>; > - clocks = <&clk_uart>; > - no-loopback-test; > - status = "disabled"; > - }; > - > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; >