Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933742AbdLRMQN (ORCPT ); Mon, 18 Dec 2017 07:16:13 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:34819 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933474AbdLRMQJ (ORCPT ); Mon, 18 Dec 2017 07:16:09 -0500 X-Google-Smtp-Source: ACJfBou30FNCzJ7mNwxMAheCyTUndPZBHQTNeumOmJOi3VEdKhrkLBJXiEtK+yb7j27bE7C8vvrnqg== From: Jacob Chen To: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mchehab@kernel.org, linux-media@vger.kernel.org, sakari.ailus@linux.intel.com, hans.verkuil@cisco.com, tfiga@chromium.org, zhengsq@rock-chips.com, laurent.pinchart@ideasonboard.com, zyc@rock-chips.com, eddie.cai.linux@gmail.com, jeffy.chen@rock-chips.com, allon.huang@rock-chips.com, devicetree@vger.kernel.org, heiko@sntech.de, robh+dt@kernel.org, Joao.Pinto@synopsys.com, Luis.Oliveira@synopsys.com, Jose.Abreu@synopsys.com, Jacob Chen Subject: [PATCH v4 15/16] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Date: Mon, 18 Dec 2017 20:14:44 +0800 Message-Id: <20171218121445.6086-12-jacob-chen@iotwrt.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218121445.6086-1-jacob-chen@iotwrt.com> References: <20171218121445.6086-1-jacob-chen@iotwrt.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1006 Lines: 33 From: Shunqian Zheng It's a Designware MIPI D-PHY, used for ISP0 in rk3399. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 66a912fab5dd..8ef321f03010 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1292,6 +1292,16 @@ status = "disabled"; }; + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; + }; + u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; -- 2.15.1