Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758681AbdLROMB (ORCPT ); Mon, 18 Dec 2017 09:12:01 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:37779 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758373AbdLROLy (ORCPT ); Mon, 18 Dec 2017 09:11:54 -0500 X-Google-Smtp-Source: ACJfBougZ3RBLdXxXMSDn8AdpNYdEom5CN0aOUpQ4CtD2b4hh8HQ80zwUzM7EzB93fffkMrAN4dFtQ== From: Philipp Rossak To: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, sean@mess.org, p.zabel@pengutronix.de, andi.shyti@samsung.com Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller Date: Mon, 18 Dec 2017 15:11:42 +0100 Message-Id: <20171218141146.23746-3-embed3d@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171218141146.23746-1-embed3d@gmail.com> References: <20171218141146.23746-1-embed3d@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1119 Lines: 32 This patch updates documentation for Device-Tree bindings for sunxi IR controller and adds the new optional property for the base clock frequency. Signed-off-by: Philipp Rossak --- Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt index 91648c569b1e..3d7f18780fae 100644 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt @@ -11,6 +11,8 @@ Required properties: Optional properties: - linux,rc-map-name: see rc.txt file in the same directory. - resets : phandle + reset specifier pair +- clock-frequency : IR Receiver clock frequency, in Herz. Defaults to 8 MHz + if missing. Example: @@ -18,6 +20,7 @@ ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; + clock-frequency = <3000000>; resets = <&apb0_rst 1>; interrupts = <0 5 1>; reg = <0x01C21800 0x40>; -- 2.11.0