Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934965AbdLRQAQ (ORCPT ); Mon, 18 Dec 2017 11:00:16 -0500 Received: from mail.linuxfoundation.org ([140.211.169.12]:37618 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934923AbdLRQAL (ORCPT ); Mon, 18 Dec 2017 11:00:11 -0500 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ram Amrani , Yuval Mintz , "David S. Miller" , Sasha Levin Subject: [PATCH 4.9 057/177] qed: Align CIDs according to DORQ requirement Date: Mon, 18 Dec 2017 16:48:00 +0100 Message-Id: <20171218152912.888958458@linuxfoundation.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218152909.823644066@linuxfoundation.org> References: <20171218152909.823644066@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1484 Lines: 41 4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ram Amrani [ Upstream commit f3e48119b97f56fb09310c95d49da122a27003d7 ] The Doorbell HW block can be configured at a granularity of 16 x CIDs, so we need to make sure that the actual number of CIDs configured would be a multiplication of 16. Today, when RoCE is enabled - given that the number is unaligned, doorbelling the higher CIDs would fail to reach the firmware and would eventually timeout. Fixes: dbb799c39717 ("qed: Initialize hardware for new protocols") Signed-off-by: Ram Amrani Signed-off-by: Yuval Mintz Signed-off-by: David S. Miller Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/qlogic/qed/qed_cxt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c +++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c @@ -373,8 +373,9 @@ static void qed_cxt_set_proto_cid_count( u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; u32 cxt_size = CONN_CXT_SIZE(p_hwfn); u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; + u32 align = elems_per_page * DQ_RANGE_ALIGN; - p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page); + p_conn->cid_count = roundup(p_conn->cid_count, align); } }