Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938191AbdLSEAE (ORCPT ); Mon, 18 Dec 2017 23:00:04 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:37038 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934871AbdLSD74 (ORCPT ); Mon, 18 Dec 2017 22:59:56 -0500 X-Google-Smtp-Source: ACJfBou2FTOIZuQNhQTN1h89PKFDV6Mr6gdJFGXUNlglXEBl/x2IN6EE6mJ1bUwuYbvVkVMNk3LNnw== From: Dmitry Osipenko To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] clk: tegra20: Correct PLL_C_OUT1 setup Date: Tue, 19 Dec 2017 06:59:07 +0300 Message-Id: <8b4c10318e696cc928ad0e528004a7aed72d6c61.1513655733.git.digetx@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <10b27ad57c959b6a87f339cc2237cfe45865771d.1513655733.git.digetx@gmail.com> References: <10b27ad57c959b6a87f339cc2237cfe45865771d.1513655733.git.digetx@gmail.com> In-Reply-To: <10b27ad57c959b6a87f339cc2237cfe45865771d.1513655733.git.digetx@gmail.com> References: <10b27ad57c959b6a87f339cc2237cfe45865771d.1513655733.git.digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1365 Lines: 32 PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's set it to 240 MHz and explicitly specify HCLK rate for consistency. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver --- Change log: v2: No change. drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index d143a867968a..06c743988ae2 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1019,9 +1019,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 0 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 0 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, -- 2.15.1