Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938283AbdLSG4C (ORCPT ); Tue, 19 Dec 2017 01:56:02 -0500 Received: from mail-by2nam01on0040.outbound.protection.outlook.com ([104.47.34.40]:15107 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932857AbdLSGz4 (ORCPT ); Tue, 19 Dec 2017 01:55:56 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Linu.Cherian@cavium.com; Date: Tue, 19 Dec 2017 12:25:24 +0530 From: Linu Cherian To: Marc Zyngier Cc: Robin Murphy , Linu Cherian , Neil Leeder , Will Deacon , Mark Rutland , Mark Langsdorf , Jon Masters , Timur Tabi , linux-kernel@vger.kernel.org, Mark Brown , Mark Salter , linux-arm-kernel@lists.infradead.org, Sunil.Goutham@cavium.com, ynorov@caviumnetworks.com Subject: Re: [PATCH 0/2] arm64 SMMUv3 PMU driver with IORT support Message-ID: <20171219065524.GB13415@virtx40> References: <1501876754-1064-1-git-send-email-nleeder@codeaurora.org> <20171210023549.GA22492@virtx40> <999b7132-2de8-2872-1067-fc7e02cbc57a@arm.com> <7312293d-8897-95d8-9045-9e97a6c150eb@arm.com> MIME-Version: 1.0 Content-Type: text/plain; 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IIRC resizing a possibly-live ITT is a > > right pain in the bum to do - is it just that? > > Understatement of the day! ;-) Yes, it is a massive headache, and will > either result in a temporary loss of interrupts (at some point you have > to unmap the ITT), or with spurious interrupts (you generate interrupts > for all the MSIs you've blackholed when unmapping the ITT). Just sharing a thought. If the firmware, through device tree/ACPI can provide the following input to the ITS driver, (For example, as part of msi-parent property in device tree) 1. flag indicating the ITT (Device ID) is being shared 2. the maximum number of vectors that are required to be allocated for this ITT resizing of ITT and the associated complexities could be avoided. > > > > >> We were looking into the option of keeping the SMMU PMCG nodes as sub nodes under > >> SMMUv3 node, so that SMMUv3 driver could probe and figure out the total vectors > >> required for SMMU PMCG devices and make a common platform_msi_domain_alloc/free_irqs > >> function call for all devices that share the platform bus id. > > > > I'm not sure how scalable that approach would be, since it's not > > entirely obvious how to handle PMCGs associated with named components or > > root complexes (rather than directly with SMMU instances). We certainly > > don't want to end up spraying similar PMCG DevID logic around all manner > > of GPU/accelerator/etc. drivers in future (whilst PMCGs for device TLBs > > will be expected to have distinct IDs from their host devices, they > > could reasonably still overlap with other PMCGs/SMMUs). > > > >> Would like to know your expert opinion on what would be the right approach > >> to handle this case ? > > > > My gut feeling says the way to deal with this properly is in the ITS > > code, but I appreciate that that's a lot easier said than done :/ > > I can revive the hack I once wrote for that (and that was hoping to > forever forget), but that's pretty disgusting, and subject to the above > caveat. > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... -- Linu cherian