Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760269AbdLSIJ7 (ORCPT ); Tue, 19 Dec 2017 03:09:59 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36789 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760185AbdLSIJw (ORCPT ); Tue, 19 Dec 2017 03:09:52 -0500 X-Google-Smtp-Source: ACJfBovbY2x6aVS3N7g+Iqn2TG3AhFro/CuYQ715gRcrYe5MoFJACkv5+fN8S8tzqi2B6TJiYnKzvw== From: Zong Li To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, palmer@sifive.com, albert@sifive.com, linux-kernel@vger.kernel.org, patches@groups.riscv.org, greentime@andestech.com, zong@andestech.com Cc: Zong Li Subject: [PATCH] irqchip/riscv-plic: fix address alignment of the plic enable bits Date: Tue, 19 Dec 2017 15:44:38 +0800 Message-Id: <1513669478-32438-1-git-send-email-zongbox@gmail.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2153 Lines: 59 When the interrupt sourece id > 31, the register address is not 4 byte alignment. Arithmetic on void pointer has no size extension, it just add the result of 'hwirq/32' directly. Signed-off-by: Zong Li --- drivers/irqchip/irq-riscv-plic.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-plic.c b/drivers/irqchip/irq-riscv-plic.c index b5182b4..0a43763 100644 --- a/drivers/irqchip/irq-riscv-plic.c +++ b/drivers/irqchip/irq-riscv-plic.c @@ -92,6 +92,8 @@ */ #define ENABLE_BASE 0x2000 #define ENABLE_PER_HART 0x80 +#define ENABLE_SOURCES 32 +#define ENABLE_SOURCES_OFFSET 4 /* * Each hart context has a set of control registers associated with it. Right @@ -128,9 +130,10 @@ struct plic_data { /* Addressing helper functions. */ static inline -void __iomem *plic_enable_vector(struct plic_data *data, int contextid) +void __iomem *plic_enable_vector(struct plic_data *data, int contextid, int hwirq) { - return data->reg + ENABLE_BASE + contextid * ENABLE_PER_HART; + return data->reg + ENABLE_BASE + contextid * ENABLE_PER_HART + + (hwirq / ENABLE_SOURCES) * ENABLE_SOURCES_OFFSET; } static inline @@ -172,8 +175,8 @@ void plic_complete(struct plic_data *data, int contextid, u32 claim) /* Explicit interrupt masking. */ static void plic_disable(struct plic_data *data, int contextid, int hwirq) { - void __iomem *reg = plic_enable_vector(data, contextid) + (hwirq / 32); - u32 mask = ~(1 << (hwirq % 32)); + void __iomem *reg = plic_enable_vector(data, contextid, hwirq); + u32 mask = ~(1 << (hwirq % ENABLE_SOURCES)); spin_lock(&data->lock); writel(readl(reg) & mask, reg); @@ -182,8 +185,8 @@ static void plic_disable(struct plic_data *data, int contextid, int hwirq) static void plic_enable(struct plic_data *data, int contextid, int hwirq) { - void __iomem *reg = plic_enable_vector(data, contextid) + (hwirq / 32); - u32 bit = 1 << (hwirq % 32); + void __iomem *reg = plic_enable_vector(data, contextid, hwirq); + u32 bit = 1 << (hwirq % ENABLE_SOURCES); spin_lock(&data->lock); writel(readl(reg) | bit, reg); -- 2.7.4