Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752633AbdLSWFo convert rfc822-to-8bit (ORCPT ); Tue, 19 Dec 2017 17:05:44 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15310 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750859AbdLSWFk (ORCPT ); Tue, 19 Dec 2017 17:05:40 -0500 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 19 Dec 2017 14:06:29 -0800 Subject: Re: [PATCH 1/2] drm/nouveau/bar/gf100: fix hang when calling ->fini() before ->init() From: Jon Hunter To: Guillaume Tucker , Ben Skeggs CC: David Airlie , , , , References: <6db622ac-319d-c640-91ab-9248e528b69b@nvidia.com> Message-ID: <6138a5ee-74e0-350a-ffc0-239bf3275914@nvidia.com> Date: Tue, 19 Dec 2017 22:05:34 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.26.11.57] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4262 Lines: 108 On 06/12/17 17:18, Jon Hunter wrote: > > On 06/12/17 09:22, Guillaume Tucker wrote: >> On 05/12/17 18:32, Ben Skeggs wrote: >>> On Wed, Dec 6, 2017 at 12:30 AM, Jon Hunter wrote: >>> >>>> >>>> On 04/12/17 18:37, Guillaume Tucker wrote: >>>>> If the firmware fails to load then ->fini() will be called before the >>>>> device has been initialised, causing the kernel to hang while trying >>>>> to write to a register.  Add a test in ->fini() to avoid this issue. >>>>> >>>>> This fixes a kernel hang on tegra124. >>>>> >>>>> Fixes: b17de35a2ebbe ("drm/nouveau/bar: implement bar1 teardown") >>>>> Signed-off-by: Guillaume Tucker >>>>> CC: Ben Skeggs >>>>> --- >>>>>  drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 7 +++++-- >>>>>  1 file changed, 5 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c >>>> b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c >>>>> index a3ba7f50198b..95e2aba64aad 100644 >>>>> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c >>>>> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c >>>>> @@ -43,9 +43,12 @@ gf100_bar_bar1_wait(struct nvkm_bar *base) >>>>>  } >>>>> >>>>>  void >>>>> -gf100_bar_bar1_fini(struct nvkm_bar *bar) >>>>> +gf100_bar_bar1_fini(struct nvkm_bar *base) >>>>>  { >>>>> -     nvkm_mask(bar->subdev.device, 0x001704, 0x80000000, 0x00000000); >>>>> +     struct nvkm_device *device = base->subdev.device; >>>>> + >>>>> +     if (base->subdev.oneinit) >>>>> +             nvkm_mask(device, 0x001704, 0x80000000, 0x00000000); >>>>>  } >>>>> >>>>>  void >>>> >>>> I have tested this and it works for me. Thanks for fixing this! Would be >>>> good to get Ben's ACK, but you can have my ... >>>> >>> I'd love to get a good explanation as to why it hangs without this >>> change, >>> as, on the surface, it's not immediately obvious as to why it's hanging. >> >> To be fair I'm not entirely sure either why this causes a hang, I >> haven't read the TRM...  The iomem has been mapped at this point, >> so accessing the register should work.  One clue is when you look >> at _bar1_init(), the 0x1704 register is initialised with >> some (device instance?) memory address.  So it's possible that >> the hardware does something special when you set this to 0 as in >> _bar1_fini(), which may fail in particular if it was previously >> not initialised with a valid address. >> >> This is merely guesswork, would be interested to find out the >> real explanation though. > > OK, well that's no good. It's a good pointer, but we need to make sure > we understand the root of this hang. I will see if I have sometime to > dig into this further, maybe next week. I spent a bit of time looking at this, but I still do not fully understand the cause of the hang. It appears to hang initialisation of the FB subdev and it appears to be around the point where the L2 cache is flushed. I will see if anyone else has a clue what is happening here. Ben, in the meantime with the holiday season upon us, should we remove the bar1 teardown for gk20a? diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 9646adec57cb..243f0a5c8a62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -73,7 +73,8 @@ struct nvkm_vmm * nvkm_bar_fini(struct nvkm_subdev *subdev, bool suspend) { struct nvkm_bar *bar = nvkm_bar(subdev); - bar->func->bar1.fini(bar); + if (bar->func->bar1.fini) + bar->func->bar1.fini(bar); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c index b10077d38839..35878fb538f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -26,7 +26,6 @@ .dtor = gf100_bar_dtor, .oneinit = gf100_bar_oneinit, .bar1.init = gf100_bar_bar1_init, - .bar1.fini = gf100_bar_bar1_fini, .bar1.wait = gf100_bar_bar1_wait, .bar1.vmm = gf100_bar_bar1_vmm, .flush = g84_bar_flush, Cheers Jon -- nvpublic