Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754420AbdLTDZ2 (ORCPT ); Tue, 19 Dec 2017 22:25:28 -0500 Received: from mail-pg0-f67.google.com ([74.125.83.67]:46867 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754396AbdLTDZY (ORCPT ); Tue, 19 Dec 2017 22:25:24 -0500 X-Google-Smtp-Source: ACJfBosrhrCcW5jYNa07zHAb3KJ2bnywp9Ij6nd9myueFzgDfFViwA1+5iKR0ZNA3vML0DWpjy1GXg== From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 09/20] ARM: dts: aspeed: Add PWM and tachometer node Date: Wed, 20 Dec 2017 13:53:17 +1030 Message-Id: <20171220032328.30584-10-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171220032328.30584-1-joel@jms.id.au> References: <20171220032328.30584-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1638 Lines: 56 The PWM/tach unit has a clock and reset phandle. It needs both in order to function correctly. Signed-off-by: Joel Stanley -- v3: Add the pwm reset phandle --- arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index d2a82850b05b..91aea96c10c8 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -189,6 +189,16 @@ clocks = <&syscon ASPEED_CLK_APB>; }; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2400-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; + vuart: serial@1e787000 { compatible = "aspeed,ast2400-vuart"; reg = <0x1e787000 0x40>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 3a25fa48d4f6..af3869ec87bb 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -239,6 +239,16 @@ status = "disabled"; }; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_PWM>; + status = "disabled"; + }; + vuart: serial@1e787000 { compatible = "aspeed,ast2500-vuart"; reg = <0x1e787000 0x40>; -- 2.15.1