Date: Wed, 20 Dec 2017 19:26:51 +0300
From: Jan Dakinevich <jan.dakinevich@virtuozzo.com>
To: <linux-kernel@vger.kernel.org>
Cc: "Denis V . Lunev" <den@virtuozzo.com>,
        Roman Kagan <rkagan@virtuozzo.com>,
        Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>, "H. Peter Anvin" <hpa@zytor.com>,
        <x86@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,
        Radim =?UTF-8?B?S3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        Andi Kleen <ak@linux.intel.com>, Kan Liang <kan.liang@intel.com>,
        Colin King <colin.king@canonical.com>,
        Stephane Eranian <eranian@google.com>,
        Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jin Yao <yao.jin@linux.intel.com>, <kvm@vger.kernel.org>
Subject: Re: [PATCH RFC 0/2] ignore LBR-related MSRs
Message-ID: <20171220192651.6063461a@virtuozzo.com>
In-Reply-To: <1512560585-27263-1-git-send-email-jan.dakinevich@virtuozzo.com>
References: <1512560585-27263-1-git-send-email-jan.dakinevich@virtuozzo.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2017 16:26:52.9288 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6e64a44e-5779-47c1-49f3-08d547c67bc4
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 0bc7f26d-0264-416e-a6fc-8352af79c58f
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0801MB2739
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Content-Length: 1291
Lines: 37

On Wed, 6 Dec 2017 14:43:01 +0300
Jan Dakinevich <jan.dakinevich@virtuozzo.com> wrote:

> w2k16 essentials fails to boot if underlying hypervisor lacks of
> support for LBR MSRs. To workaround the issue, it suggessted to
> ignore these MSRs (but not all).
> 
> The information, which MSRs are supported for specific platform is
> taken from perf, it is the subject of the first patch. The second
> patch adds ignoring for these MSRs to pmu_intel code of KVM.
> 
> TODO: use MSR load/store areas to make full support of LBR debug.
> 
> Jan Dakinevich (2):
>   perf/x86/intel: make reusable LBR initialization code
>   KVM: x86/vPMU: ignore access to LBR-related MSRs
> 
>  arch/x86/events/core.c            |   8 +-
>  arch/x86/events/intel/core.c      |  59 +++------
>  arch/x86/events/intel/lbr.c       | 272
> +++++++++++++++++++++++++-------------
> arch/x86/events/perf_event.h      |  27 +---
> arch/x86/include/asm/kvm_host.h   |   2 +
> arch/x86/include/asm/perf_event.h |  11 ++
> arch/x86/kvm/pmu_intel.c          |  33 +++++ 7 files changed, 250
> insertions(+), 162 deletions(-)
> 

ping

Please, tell me whether these patches are applicable (as KVM workaround)
or it is assumed they should be reworked following to recommendation by
Andi Kleen?

-- 
Best regards
Jan Dakinevich