Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756410AbdLTTkN (ORCPT ); Wed, 20 Dec 2017 14:40:13 -0500 Received: from mail-it0-f65.google.com ([209.85.214.65]:46219 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755534AbdLTTkI (ORCPT ); Wed, 20 Dec 2017 14:40:08 -0500 X-Google-Smtp-Source: ACJfBovQQOTX+Hp8hF8T8elbl7gCkgkJEBKqSm+H//xbJkYCSYmUTaPbQnH/WuMLWr5LduIRmhutS0ZDUhKEcXLLSJM= MIME-Version: 1.0 In-Reply-To: <1513771538-41693-3-git-send-email-pbonzini@redhat.com> References: <1513771538-41693-1-git-send-email-pbonzini@redhat.com> <1513771538-41693-3-git-send-email-pbonzini@redhat.com> From: Jim Mattson Date: Wed, 20 Dec 2017 11:40:07 -0800 Message-ID: Subject: Re: [PATCH 2/3] KVM: vmx: simplify MSR bitmap setup To: Paolo Bonzini Cc: LKML , kvm list , David Hildenbrand Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1833 Lines: 43 This doesn't look right to me. Without APIC-register virtualization, the only X2APIC MSR intercept that should be disabled is TPR. On Wed, Dec 20, 2017 at 4:05 AM, Paolo Bonzini wrote: > The APICv-enabled MSR bitmap is a superset of the APICv-disabled bitmap. > Make that obvious in vmx_disable_intercept_msr_x2apic. > > Signed-off-by: Paolo Bonzini > --- > arch/x86/kvm/vmx.c | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index 9f9c3194440f..905aaa778306 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -5263,12 +5263,9 @@ static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_activ > msr, type); > __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, > msr, type); > - } else { > - __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, > - msr, type); > - __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, > - msr, type); > } > + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, msr, type); > + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, msr, type); > } > > static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) > @@ -7148,7 +7145,6 @@ static __init int hardware_setup(void) > * TPR reads and writes can be virtualized even if virtual interrupt > * delivery is not in use. > */ > - vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); > vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); > > /* EOI */ > -- > 1.8.3.1 > >