Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752267AbdLUJLH (ORCPT ); Thu, 21 Dec 2017 04:11:07 -0500 Received: from mga06.intel.com ([134.134.136.31]:13915 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752107AbdLUJKE (ORCPT ); Thu, 21 Dec 2017 04:10:04 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,435,1508828400"; d="scan'208";a="15443219" Subject: Re: [PATCH 05/12] mmc: sdhci-omap: Workaround for Errata i802 To: Kishon Vijay Abraham I , Ulf Hansson , Rob Herring , Tony Lindgren Cc: Mark Rutland , Russell King , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, nsekhar@ti.com References: <20171214130941.26666-1-kishon@ti.com> <20171214130941.26666-6-kishon@ti.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <8ada81f8-7e67-8d77-471a-502f6ec10b2b@intel.com> Date: Thu, 21 Dec 2017 11:09:35 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20171214130941.26666-6-kishon@ti.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2044 Lines: 56 On 14/12/17 15:09, Kishon Vijay Abraham I wrote: > Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1 > (SPRZ429K July 2014–Revised March 2017 [1]) mentions > DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur > during the tuning procedure and it has to be disabled during the > tuning procedure Implement workaround for Errata i802 here.. > > [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf > > Signed-off-by: Kishon Vijay Abraham I Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-omap.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c > index df8a0a472996..b20f4c79ccc6 100644 > --- a/drivers/mmc/host/sdhci-omap.c > +++ b/drivers/mmc/host/sdhci-omap.c > @@ -266,6 +266,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) > struct sdhci_pltfm_host *pltfm_host; > struct sdhci_omap_host *omap_host; > struct device *dev; > + u32 ier = host->ier; > > pltfm_host = sdhci_priv(host); > omap_host = sdhci_pltfm_priv(pltfm_host); > @@ -283,6 +284,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) > reg |= DLL_SWT; > sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); > > + /* > + * OMAP5/DRA74X/DRA72x Errata i802: > + * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur > + * during the tuning procedure. So disable it during the > + * tuning procedure. > + */ > + ier &= ~SDHCI_INT_DATA_CRC; > + sdhci_writel(host, ier, SDHCI_INT_ENABLE); > + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); > + > while (phase_delay <= MAX_PHASE_DELAY) { > sdhci_omap_set_dll(omap_host, phase_delay); > > @@ -328,6 +339,8 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) > > ret: > sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); > + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); > + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); > return ret; > } > >