Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753214AbdLUSGN (ORCPT ); Thu, 21 Dec 2017 13:06:13 -0500 Received: from mail-io0-f196.google.com ([209.85.223.196]:40391 "EHLO mail-io0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751705AbdLUSGK (ORCPT ); Thu, 21 Dec 2017 13:06:10 -0500 X-Google-Smtp-Source: ACJfBotNRp3WTHCEU8Zh0rvOf7SMPXfvC5wis7/VbDQ3EvH0cqhLFxLyOm0vYvIfIEMAavsCMNL1b3yLvPCtmWc3KMA= MIME-Version: 1.0 In-Reply-To: <1513857062-44013-3-git-send-email-pbonzini@redhat.com> References: <1513857062-44013-1-git-send-email-pbonzini@redhat.com> <1513857062-44013-3-git-send-email-pbonzini@redhat.com> From: Jim Mattson Date: Thu, 21 Dec 2017 10:06:08 -0800 Message-ID: Subject: Re: [PATCH 2/3] KVM: vmx: simplify MSR bitmap setup To: Paolo Bonzini Cc: LKML , kvm list , David Hildenbrand Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2128 Lines: 51 Reviewed-by: Jim Mattson On Thu, Dec 21, 2017 at 3:51 AM, Paolo Bonzini wrote: > The APICv-enabled MSR bitmap passes through all MSRs in the > APICv-disabled bitmap (and then some). Make that obvious in > vmx_disable_intercept_msr_x2apic. > > Signed-off-by: Paolo Bonzini > --- > v1->v2: included the right version of the patch > > arch/x86/kvm/vmx.c | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index 2b27afc93cb4..68239aabec52 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -5257,14 +5257,13 @@ static void pt_disable_intercept_for_msr(bool flag) > } > } > > -static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active) > +static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_only) > { > - if (apicv_active) { > - __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, > - msr, type); > - __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, > - msr, type); > - } else { > + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv, > + msr, type); > + __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv, > + msr, type); > + if (!apicv_only) { > __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, > msr, type); > __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, > @@ -7149,7 +7148,6 @@ static __init int hardware_setup(void) > * TPR reads and writes can be virtualized even if virtual interrupt > * delivery is not in use. > */ > - vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true); > vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false); > > /* EOI */ > -- > 1.8.3.1 > >