Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755840AbdLVAYi (ORCPT ); Thu, 21 Dec 2017 19:24:38 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:54310 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755753AbdLVAYS (ORCPT ); Thu, 21 Dec 2017 19:24:18 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A4C8960328 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Thu, 21 Dec 2017 16:24:16 -0800 From: Stephen Boyd To: Abhishek Sahu Cc: Michael Turquette , Rob Herring , Andy Gross , David Brown , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 10/11] dt-bindings: clock: qcom: add misc resets for PCIE and NSS Message-ID: <20171222002416.GT7997@codeaurora.org> References: <1513175142-3702-1-git-send-email-absahu@codeaurora.org> <1513175142-3702-11-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1513175142-3702-11-git-send-email-absahu@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 375 Lines: 13 On 12/13, Abhishek Sahu wrote: > PCIE and NSS has MISC reset register in which single register has > multiple reset bit. The patch adds the DT bindings for these MISC > resets. > > Signed-off-by: Abhishek Sahu > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project