Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758171AbdLVKbW (ORCPT ); Fri, 22 Dec 2017 05:31:22 -0500 Received: from mga14.intel.com ([192.55.52.115]:3654 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757656AbdLVKbL (ORCPT ); Fri, 22 Dec 2017 05:31:11 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,440,1508828400"; d="scan'208";a="4765020" From: "Kogut, Jaroslaw" To: Anshuman Khandual , "linux-kernel@vger.kernel.org" , Ross Zwisler CC: "Anaczkowski, Lukasz" , "Box, David E" , "Koss, Marcin" , "Koziej, Artur" , "Lahtinen, Joonas" , "Moore, Robert" , "Nachimuthu, Murugasamy" , "Odzioba, Lukasz" , "Wysocki, Rafael J" , "Rafael J. Wysocki" , "Schmauss, Erik" , "Verma, Vishal L" , "Zheng, Lv" , Andrew Morton , Balbir Singh , Brice Goglin , "Williams, Dan J" , "Hansen, Dave" , Jerome Glisse , John Hubbard , Len Brown , Tim Chen , "devel@acpica.org" , "linux-acpi@vger.kernel.org" , "linux-mm@kvack.org" , "linux-nvdimm@lists.01.org" Subject: RE: [PATCH v3 0/3] create sysfs representation of ACPI HMAT Thread-Topic: [PATCH v3 0/3] create sysfs representation of ACPI HMAT Thread-Index: AQHTdIC5H2OC9h8kVUiEM9qurVhxxqNOu5yAgABWZ7A= Date: Fri, 22 Dec 2017 10:31:05 +0000 Message-ID: <34EF90DF7C7F0647A403B771519912C7F5382CF3@irsmsx111.ger.corp.intel.com> References: <20171214021019.13579-1-ross.zwisler@linux.intel.com> <2d6420f7-0a95-adfe-7390-a2aea4385ab2@linux.vnet.ibm.com> In-Reply-To: <2d6420f7-0a95-adfe-7390-a2aea4385ab2@linux.vnet.ibm.com> Accept-Language: pl-PL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTdlMzM4OTQtZWI0Mi00ZTgzLWJiYTQtOTc1ZjljYzk5MTc4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX1BVQkxJQyJ9XX1dfSwiU3ViamVjdExhYmVscyI6W10sIlRNQ1ZlcnNpb24iOiIxNy4yLjUuMTgiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRU1aTjBuWXRjdjhLUWtMVmdkc0RjY2ZydE9CUis0YmQxUzdXTGw2UDBHMU1KNFFscDlLMXgyb01JNVBiSVJjZCJ9 x-ctpclassification: CTP_PUBLIC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id vBMAVQbc000590 Content-Length: 6522 Lines: 122 > ... first thinking about redesigning the NUMA for > heterogeneous memory may not be a good idea. Will look into this further. I agree with comment that first a direction should be defined how to handle heterogeneous memory system. > https://linuxplumbersconf.org/2017/ocw//system/presentations/4656/original/ > Hierarchical_NUMA_Design_Plumbers_2017.pdf I miss in the presentation a user perspective of the new approach, e.g. - How does application developer see/understand the heterogeneous memory system? - How does app developer use the heterogeneous memory system? - What are modification in API/sys interfaces? In other hand, if we assume that separate memory NUMA node has different memory capabilities/attributes from stand point of particular CPU, it is easy to explain for user how to describe/handle heterogeneous memory. Of course, current numa design is not sufficient in kernel in following areas today: - Exposing memory attributes that describe heterogeneous memory system - Interfaces to use the heterogeneous memory system, e.g. more sophisticated policies - Internal mechanism in memory management, e.g. automigration, maybe something else. > -----Original Message----- > From: Anshuman Khandual [mailto:khandual@linux.vnet.ibm.com] > Sent: Friday, December 22, 2017 4:10 AM > To: Ross Zwisler ; linux-kernel@vger.kernel.org > Cc: Anaczkowski, Lukasz ; Box, David E > ; Kogut, Jaroslaw ; Koss, > Marcin ; Koziej, Artur ; > Lahtinen, Joonas ; Moore, Robert > ; Nachimuthu, Murugasamy > ; Odzioba, Lukasz > ; Wysocki, Rafael J ; > Rafael J. Wysocki ; Schmauss, Erik > ; Verma, Vishal L ; > Zheng, Lv ; Andrew Morton foundation.org>; Balbir Singh ; Brice Goglin > ; Williams, Dan J ; > Hansen, Dave ; Jerome Glisse ; > John Hubbard ; Len Brown ; Tim > Chen ; devel@acpica.org; linux- > acpi@vger.kernel.org; linux-mm@kvack.org; linux-nvdimm@lists.01.org > Subject: Re: [PATCH v3 0/3] create sysfs representation of ACPI HMAT > > On 12/14/2017 07:40 AM, Ross Zwisler wrote: > > ==== Quick Summary ==== > > > > Platforms exist today which have multiple types of memory attached to > > a single CPU. These disparate memory ranges have some characteristics > > in common, such as CPU cache coherence, but they can have wide ranges > > of performance both in terms of latency and bandwidth. > > Right. > > > > > For example, consider a system that contains persistent memory, > > standard DDR memory and High Bandwidth Memory (HBM), all attached to > the same CPU. > > There could potentially be an order of magnitude or more difference in > > performance between the slowest and fastest memory attached to that CPU. > > Right. > > > > > With the current Linux code NUMA nodes are CPU-centric, so all the > > memory attached to a given CPU will be lumped into the same NUMA node. > > This makes it very difficult for userspace applications to understand > > the performance of different memory ranges on a given CPU. > > Right but that might require fundamental changes to the NUMA > representation. > Plugging those memory as separate NUMA nodes, identify them through sysfs > and try allocating from it through mbind() seems like a short term solution. > > Though if we decide to go in this direction, sysfs interface or something similar > is required to enumerate memory properties. > > > > > We solve this issue by providing userspace with performance > > information on individual memory ranges. This performance information > > is exposed via > > sysfs: > > > > # grep . mem_tgt2/* mem_tgt2/local_init/* 2>/dev/null > > mem_tgt2/firmware_id:1 > > mem_tgt2/is_cached:0 > > mem_tgt2/local_init/read_bw_MBps:40960 > > mem_tgt2/local_init/read_lat_nsec:50 > > mem_tgt2/local_init/write_bw_MBps:40960 > > mem_tgt2/local_init/write_lat_nsec:50 > > I might have missed discussions from earlier versions, why we have this kind of > a "source --> target" model ? We will enlist properties for all possible "source -- > > target" on the system ? Right now it shows only bandwidth and latency > properties, can it accommodate other properties as well in future ? > > > > > This allows applications to easily find the memory that they want to use. > > We expect that the existing NUMA APIs will be enhanced to use this new > > information so that applications can continue to use them to select > > their desired memory. > > I had presented a proposal for NUMA redesign in the Plumbers Conference this > year where various memory devices with different kind of memory attributes > can be represented in the kernel and be used explicitly from the user space. > Here is the link to the proposal if you feel interested. The proposal is very > intrusive and also I dont have a RFC for it yet for discussion here. > > https://linuxplumbersconf.org/2017/ocw//system/presentations/4656/original/ > Hierarchical_NUMA_Design_Plumbers_2017.pdf > > Problem is, designing the sysfs interface for memory attribute detection from > user space without first thinking about redesigning the NUMA for > heterogeneous memory may not be a good idea. Will look into this further. -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. 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