Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751145AbdL0F6P (ORCPT ); Wed, 27 Dec 2017 00:58:15 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:25253 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750762AbdL0F6L (ORCPT ); Wed, 27 Dec 2017 00:58:11 -0500 DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20171227055809epoutp04dae76c624c9743fb1ea4782097cf6d0a~EETPeU-he2307323073epoutp04i X-AuditID: b6c32a46-995ff700000010ee-37-5a433670b36f From: Jaehoon Chung Subject: Re: [RFC 2/2] pci: dwc: pci-exynos: add the codes to support the exynos5433 To: Rob Herring Cc: linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krzk@kernel.org, jingoohan1@gmail.com, kgene@kernel.org, lorenzo.pieralisi@arm.com Message-id: Date: Wed, 27 Dec 2017 14:58:08 +0900 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-version: 1.0 In-reply-to: <20171226211123.feje5l46y62aft7u@rob-hp-laptop> Content-type: text/plain; charset="utf-8" Content-language: en-US Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA01SfUgTcRjut7vdTmtxzdQXA7MDCS2XN7d5lkal2SIpqag0wk49nOU+2G2R BSZ9WC76sMJslRUUORniV7WsxEzU/lDD1DRwQaGIVlCGlSa1eQv87/k97/P83vd5eUlMcZEI I/ONVt5i5ApoIhB//CoqPsasTc6M7Z9Ss3fauqVs1Y8bMvbSpwmM7emplbFvm24RbFdlB8FW 9DRL2M8zYzL273O3bEOAzlXpQrqnjmGZrr66lNBN1oen45l8op7ncnlLBG/MMeXmG/OS6G27 spKzNNpYJoZJYOPpCCNn4JPolLT0mNT8Au8sdMQRrsDmpdI5QaDXrE+0mGxWPkJvEqxJ9H6G USmZ2HilSqVSquMOrFVpvJKDvP5hqRM3d2qOemYfYcVoaJUdBZBAqcH1/g6yo0BSQbkRfOwt k4iPnwgaxmvQf9UbexUmFp4heFF6wW/xIOge6sR9KoJaDU+mOiQ+HETtgfY/lwkfXkqtgJmS cqnPgFG9CG67nHPfyqn14Gmv9ZpJEqci4duIxkcHe73O6XG/ZAn8uuqZkwRQiXBycJmPxqgo GPtxBRdxKJw6M+THy6HB9WVuUKDeETD8yONPkAL3Paf9OAjGOxplIl4Go9V1fv4sgq6bQaL5 GoKqivMSsRAHo/fsErHDYjj3albmGwgoOZwrUYgSHbQ0/cZFvBG+vqz0b2sSQV3/X+IyCnfM y+OYF8IxL4RjXoi7CK9GIbxZMOTxgsqsUgqcQbAZ85Q5JkM9mrvF6FQ3ut+d1oooEtGL5GTb pkyFlDsiFBpaEZAYvVSeXL4hUyHP5QqP8RZTlsVWwAutSONddxkWFpxj8l620ZrFqBNi1Vqt Kl7Les8tVF70eGCfgsrjrPxhnjfzlv8+CRkQVoyKN2c32zG708L1RWc3pka5Uww0M9hRJJ3e 0VxREunemb/wxfeZkd/bmc7a6/DnUN9es/yYnpV+1oxLF+QkNbV3Ny5eV3Qxg94d3B+Z8O35 jN3kfqBYWeP84LaHGK3HL9Qkv55oa5F8nS7HCxduySgbmP11HsJbZkO3Jp7IKCqmcUHPMdGY ReD+ATiP54uhAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPLMWRmVeSWpSXmKPExsVy+t9jAd0CM+cog00r1SzmHznHarHiy0x2 i/7Hr5ktzp/fwG5xedccNouz846zWcw4v4/J4s3vF+wW//fsYHfg9Fgzbw2jx85Zd9k9Nq3q ZPP4vEkugCWKyyYlNSezLLVI3y6BK2N550qWghOmFff+bmVuYLyp3cXIySEhYCJxoWsFcxcj F4eQwE5GiY7dTUwQzgNGiQtLGplAqtgEdCS2fzsOZgsLhEkc+zOBDcQWEVCU+N02jRWkgVng EqPExEf/2CC6PzNK9B6eyAxSxStgJ3Hv2AaWLkYODhYBVYmPT01BwqJAg/qb/0KVCEr8mHwP rIRTwEai6YY0iMksoC4xZUouSAWzgLhEc+tNFghbXmLzmrfMExgFZiFpnoXQMQtJxywkHQsY WVYxSqYWFOem5xYbFRjlpZbrFSfmFpfmpesl5+duYgRGw7bDWv07GB8viT/EKMDBqMTDm3DM KUqINbGsuDL3EKMEB7OSCK/zNIcoId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rz8+ccihQTSE0tS s1NTC1KLYLJMHJxSDYyKUvLPH9ftLeIN77avC1e+rH2N4/UU90+ZsXZPOfW4A2a4ca/NXzJ5 oXIe+4dnxxUr5z1+FHlAuIqRQ6rpZnci59zLae8CTAXVS/XKTCOYNP6ymj4MfujLdHrJKl71 0JW3ZWc1Bh3KXp30fZnecfMK+cgvvTfeXVIR3su6nHVu0t741mnel5RYijMSDbWYi4oTAXQk DmaCAgAA X-CMS-MailID: 20171227055808epcas2p185588666a77fe53f54ca5d1d1a08700b X-Msg-Generator: CA CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47 X-RootMTR: 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47 References: <20171221121408.22636-1-jh80.chung@samsung.com> <20171221121408.22636-2-jh80.chung@samsung.com> <20171226211123.feje5l46y62aft7u@rob-hp-laptop> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 6648 Lines: 206 On 12/27/2017 06:11 AM, Rob Herring wrote: > On Thu, Dec 21, 2017 at 09:14:07PM +0900, Jaehoon Chung wrote: >> Exynos5433 has the PCIe for WiFi. >> Added the codes relevant to PCIe for supporting the exynos5433. >> Also changed the binding documentation name to >> 'samsung,exynos-pcie.txt'. >> (It's not only exynos5440 anymore.) >> >> Signed-off-by: Jaehoon Chung >> --- >> ...exynos5440-pcie.txt => samsung,exynos-pcie.txt} | 2 +- >> drivers/pci/dwc/pci-exynos.c | 183 ++++++++++++++++----- >> 2 files changed, 144 insertions(+), 41 deletions(-) >> rename Documentation/devicetree/bindings/pci/{samsung,exynos5440-pcie.txt => samsung,exynos-pcie.txt} (97%) >> >> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt >> similarity index 97% >> rename from Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt >> rename to Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt >> index 34a11bfbfb60..958dcc150505 100644 >> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt >> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt >> @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP >> and thus inherits all the common properties defined in designware-pcie.txt. >> >> Required properties: >> -- compatible: "samsung,exynos5440-pcie" >> +- compatible: "samsung,exynos5440-pcie" or "samsung,exynos5433-pcie" > > Quite a lot of driver changes for just a new compatible. It needs to distinguish between exynos5440 and other exynos variants. So needs to add the new common compatible likes "samsung,exynos5-pcie" or "samsung,exynos-pcie". Actually, i hope that exynos5440 can be removed from mainline kernel. > >> - reg: base addresses and lengths of the PCIe controller, > > For example, you're adding the DBI registers which is not documented > here. > > Perhaps it is time to remove the old phy support before adding a new > platform. Ok, I will send the patches to remove the old phy. > >> the PHY controller, additional register for the PHY controller. >> (Registers for the PHY controller are DEPRECATED. >> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c >> index 5596fdedbb94..8dee2e90347e 100644 >> --- a/drivers/pci/dwc/pci-exynos.c >> +++ b/drivers/pci/dwc/pci-exynos.c >> @@ -40,6 +40,8 @@ >> #define PCIE_IRQ_SPECIAL 0x008 >> #define PCIE_IRQ_EN_PULSE 0x00c >> #define PCIE_IRQ_EN_LEVEL 0x010 >> +#define PCIE_SW_WAKE 0x018 >> +#define PCIE_BUS_EN BIT(1) >> #define IRQ_MSI_ENABLE BIT(2) >> #define PCIE_IRQ_EN_SPECIAL 0x014 >> #define PCIE_PWR_RESET 0x018 >> @@ -49,7 +51,8 @@ >> #define PCIE_NONSTICKY_RESET 0x024 >> #define PCIE_APP_INIT_RESET 0x028 >> #define PCIE_APP_LTSSM_ENABLE 0x02c >> -#define PCIE_ELBI_RDLH_LINKUP 0x064 >> +#define PCIE_ELBI_RDLH_LINKUP 0x074 >> +#define PCIE_ELBI_XMLH_LINKUP BIT(4) >> #define PCIE_ELBI_LTSSM_ENABLE 0x1 >> #define PCIE_ELBI_SLV_AWMISC 0x11c >> #define PCIE_ELBI_SLV_ARMISC 0x120 >> @@ -94,6 +97,10 @@ >> #define PCIE_PHY_TRSV3_PD_TSV BIT(7) >> #define PCIE_PHY_TRSV3_LVCC 0x31c >> >> +/* DBI register */ >> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC >> +#define DBI_RO_WR_EN BIT(0) >> + >> struct exynos_pcie_mem_res { >> void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */ >> void __iomem *phy_base; /* DT 1st resource: PHY CTRL */ >> @@ -221,6 +228,96 @@ static const struct exynos_pcie_ops exynos5440_pcie_ops = { >> .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources, >> }; >> >> +static int exynos5433_pcie_get_mem_resources(struct platform_device *pdev, >> + struct exynos_pcie *ep) >> +{ >> + struct dw_pcie *pci = ep->pci; >> + struct device *dev = pci->dev; >> + struct resource *res; >> + >> + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); >> + if (!ep->mem_res) >> + return -ENOMEM; >> + >> + /* External Local Bus interface(ELBI) Register */ > > These are standard DW registers IIRC. So the DW core should handle this. > >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); >> + ep->mem_res->elbi_base = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(ep->mem_res->elbi_base)) >> + return PTR_ERR(ep->mem_res->elbi_base); >> + >> + /* Data Bus Interface(DBI) Register */ >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); >> + pci->dbi_base = devm_ioremap_resource(&pdev->dev, res); > > This is handled by the DW plat driver. Perhaps the DW core should handle > it too. Will fix. > > Does the 5440 really not have DBI registers or you just happen to not > need to access them? I didn't have exynso5440 TRM, do you means exynos5433? It doesn't have its own DBI register. > >> + if (IS_ERR(pci->dbi_base)) >> + return PTR_ERR(pci->dbi_base); >> + >> + return 0; >> +} >> + >> +static int exynos5433_pcie_get_clk_resources(struct exynos_pcie *ep) >> +{ >> + struct dw_pcie *pci = ep->pci; >> + struct device *dev = pci->dev; >> + >> + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL); >> + if (!ep->clk_res) >> + return -ENOMEM; >> + >> + ep->clk_res->clk = devm_clk_get(dev, "pcie"); >> + if (IS_ERR(ep->clk_res->clk)) { >> + dev_err(dev, "Failed to get pcie rc clock\n"); >> + return PTR_ERR(ep->clk_res->clk); >> + } >> + >> + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus"); >> + if (IS_ERR(ep->clk_res->bus_clk)) { >> + dev_err(dev, "Failed to get pcie bus clock\n"); >> + return PTR_ERR(ep->clk_res->bus_clk); >> + } >> + >> + return 0; >> +} > > Can't you reuse exynos5440_pcie_get_clk_resources? They appear to be the > same. Will reuse. > >> + >> +static void exynos5433_pcie_deinit_clk_resources(struct exynos_pcie *ep) >> +{ >> + clk_disable_unprepare(ep->clk_res->bus_clk); >> + clk_disable_unprepare(ep->clk_res->clk); >> +} >> + >> + >> +static int exynos5433_pcie_init_clk_resources(struct exynos_pcie *ep) >> +{ >> + struct dw_pcie *pci = ep->pci; >> + struct device *dev = pci->dev; >> + int ret; >> + >> + ret = clk_prepare_enable(ep->clk_res->clk); >> + if (ret) { >> + dev_err(dev, "cannot enable pcie rc clock"); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(ep->clk_res->bus_clk); >> + if (ret) { >> + dev_err(dev, "cannot enable pcie bus clock"); >> + goto err_bus_clk; >> + } >> + >> + return 0; >> + >> +err_bus_clk: >> + clk_disable_unprepare(ep->clk_res->clk); >> + >> + return ret; >> +} > > Ditto. Ok. Will fix. Best Regards, Jaehoon Chung > > Rob > > >