Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752721AbdL0XZo (ORCPT ); Wed, 27 Dec 2017 18:25:44 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:43062 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbdL0XZn (ORCPT ); Wed, 27 Dec 2017 18:25:43 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DB5516081C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org From: Stephen Boyd To: Lorenzo Pieralisi Cc: Jingoo Han , Joao Pinto , linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org Subject: [PATCH v2] PCI: dwc: Use {upper,lower}_32_bits() macros for clarity Date: Wed, 27 Dec 2017 15:25:40 -0800 Message-Id: <20171227232540.22341-1-sboyd@codeaurora.org> X-Mailer: git-send-email 2.15.0.374.g5f9953d2c365 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1711 Lines: 45 We have macros for getting the upper or lower 32 bits of a number. Use them here to shave a couple lines off the code and provide clarity. Signed-off-by: Stephen Boyd --- Changes from v1: * Update dw_msi_setup_msg() too * Reword commit text slightly drivers/pci/dwc/pcie-designware-host.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 81e2157a7cfb..454b8d244071 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -89,10 +89,8 @@ void dw_pcie_msi_init(struct pcie_port *pp) msi_target = virt_to_phys((void *)pp->msi_data); /* program the msi_data */ - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, - (u32)(msi_target & 0xffffffff)); - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, - (u32)(msi_target >> 32 & 0xffffffff)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, lower_32_bits(msi_target)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(msi_target)); } static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) @@ -189,8 +187,8 @@ static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) else msi_target = virt_to_phys((void *)pp->msi_data); - msg.address_lo = (u32)(msi_target & 0xffffffff); - msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); + msg.address_lo = lower_32_bits(msi_target); + msg.address_hi = upper_32_bits(msi_target); if (pp->ops->get_msi_data) msg.data = pp->ops->get_msi_data(pp, pos); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project