Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753571AbdL1N4y (ORCPT ); Thu, 28 Dec 2017 08:56:54 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:47260 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753329AbdL1N4v (ORCPT ); Thu, 28 Dec 2017 08:56:51 -0500 From: Paul Cercueil To: Ralf Baechle , Rob Herring , Michael Turquette Cc: Mark Rutland , Stephen Boyd , Maarten ter Huurne , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Paul Cercueil Subject: [PATCH v4 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Date: Thu, 28 Dec 2017 14:56:21 +0100 Message-Id: <20171228135634.30000-3-paul@crapouillou.net> In-Reply-To: <20171228135634.30000-1-paul@crapouillou.net> References: <20170702163016.6714-2-paul@crapouillou.net> <20171228135634.30000-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 884 Lines: 31 Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 2 ++ 1 file changed, 2 insertions(+) v2: No changes v3: No changes v4: No changes diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index ab393637f7b0..a2e73a6d60fd 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) div *= clk_info->div.div; rate /= div; + } else if (clk_info->type & CGU_CLK_FIXDIV) { + rate /= clk_info->fixdiv.div; } return rate; -- 2.11.0