Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755478AbdL2HyI (ORCPT ); Fri, 29 Dec 2017 02:54:08 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:38140 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755458AbdL2HyF (ORCPT ); Fri, 29 Dec 2017 02:54:05 -0500 X-Google-Smtp-Source: ACJfBosZG4306F4HdBogPeTYIEPgFmaDBSlR1dCi35+whhZW16HqhZ/ithIyN4ZNH9eP/wJU7dxiLw== From: Shunqian Zheng To: linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mchehab@kernel.org, sakari.ailus@linux.intel.com, hans.verkuil@cisco.com, tfiga@chromium.org, zhengsq@rock-chips.com, laurent.pinchart@ideasonboard.com, zyc@rock-chips.com, eddie.cai.linux@gmail.com, jeffy.chen@rock-chips.com, allon.huang@rock-chips.com, devicetree@vger.kernel.org, heiko@sntech.de, robh+dt@kernel.org, Joao.Pinto@synopsys.com, Luis.Oliveira@synopsys.com, Jose.Abreu@synopsys.com, jacob2.chen@rock-chips.com Subject: [PATCH v5 12/16] ARM: dts: rockchip: add isp node for rk3288 Date: Fri, 29 Dec 2017 15:52:54 +0800 Message-Id: <1514533978-20408-13-git-send-email-zhengsq@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1514533978-20408-1-git-send-email-zhengsq@rock-chips.com> References: <1514533978-20408-1-git-send-email-zhengsq@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1172 Lines: 39 From: Jacob Chen rk3288 have a Embedded 13M ISP Signed-off-by: Jacob Chen --- arch/arm/boot/dts/rk3288.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd24894..5dbfafb 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -962,6 +962,23 @@ status = "disabled"; }; + isp: isp@ff910000 { + compatible = "rockchip,rk3288-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>, + <&cru HCLK_ISP>, <&cru PCLK_ISP_IN>, + <&cru SCLK_ISP_JPE>; + clock-names = "clk_isp", "aclk_isp", + "hclk_isp", "pclk_isp_in", + "sclk_isp_jpe"; + assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>; + assigned-clock-rates = <400000000>, <400000000>; + power-domains = <&power RK3288_PD_VIO>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + isp_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; -- 1.9.1