Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755366AbdL2JLP (ORCPT ); Fri, 29 Dec 2017 04:11:15 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:50178 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754628AbdL2JLN (ORCPT ); Fri, 29 Dec 2017 04:11:13 -0500 From: Vignesh R To: Cyrille Pitchen , Marek Vasut CC: David Woodhouse , Brian Norris , , , , , Dinh Nguyen , Vignesh R Subject: [PATCH v2 0/2] CQSPI: Add direct mode support Date: Fri, 29 Dec 2017 14:41:01 +0530 Message-ID: <20171229091103.14436-1-vigneshr@ti.com> X-Mailer: git-send-email 2.15.1 MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 794 Lines: 23 This patch series enables use Direct access controller on Cadence QSPI which helps in accessing QSPI flash in memory mapped mode. On TI platforms, this mode has higher throughput compared to indirect access mode. Tested on TI's 66AK2G GP EVM. It would be great if this patch series could be tested SoCFPGA as well. Although, this patch should have no effect on non TI platforms as driver continues to use indirect mode when direct access memory window is less than size of connected flash. Vignesh R (2): mtd: spi-nor: cadence-quadspi: Refactor indirect read/write sequence. mtd: spi-nor: cadence-quadspi: Add support for direct access mode drivers/mtd/spi-nor/cadence-quadspi.c | 54 +++++++++++++++++++++++++---------- 1 file changed, 39 insertions(+), 15 deletions(-) -- 2.15.1