Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751397AbdL3BPG (ORCPT ); Fri, 29 Dec 2017 20:15:06 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:39333 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751254AbdL3BNl (ORCPT ); Fri, 29 Dec 2017 20:13:41 -0500 X-Google-Smtp-Source: ACJfBouItx981g769tMpLYAhzl53CQz+Z94csWUyzTSW06WpmNb0p/pbut30MvKfP5NPF9IbilMPog== From: "Bryan O'Donoghue" To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: pure.logic@nexus-software.ie, Eugeniy Paltsev Subject: [PATCH 29/33] clk: axs10x: change axs10x_pll_round_rate return logic Date: Sat, 30 Dec 2017 01:13:08 +0000 Message-Id: <1514596392-22270-30-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> References: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1141 Lines: 33 This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Eugeniy Paltsev Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/axs10x/pll_clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 27498eb..e90ae9e 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -162,7 +162,7 @@ static unsigned long axs10x_pll_round_rate(struct clk_hw *hw, const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg; if (pll_cfg[0].rate == 0) - return -EINVAL; + return 0; best_rate = pll_cfg[0].rate; -- 2.7.4