Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751246AbdL3BNk (ORCPT ); Fri, 29 Dec 2017 20:13:40 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:34980 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751075AbdL3BN2 (ORCPT ); Fri, 29 Dec 2017 20:13:28 -0500 X-Google-Smtp-Source: ACJfBosJcx7eJZ44sg3Slid0dRkGxCyn6eCUvNgr6cPSCK5b72r4L4yNxtoapMDwqzuPcW+vmmc06w== From: "Bryan O'Donoghue" To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: pure.logic@nexus-software.ie, Tony Prisk Subject: [PATCH 15/33] clk: vt8500: change vtwm_pll_round_rate() return logic Date: Sat, 30 Dec 2017 01:12:54 +0000 Message-Id: <1514596392-22270-16-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> References: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1421 Lines: 47 This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Tony Prisk --- drivers/clk/clk-vt8500.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index 43c88f6..750c087 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -610,7 +610,7 @@ static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, struct clk_pll *pll = to_clk_pll(hw); u32 filter, mul, div1, div2; long round_rate; - int ret; + int ret = 1; switch (pll->type) { case PLL_TYPE_VT8500: @@ -634,11 +634,11 @@ static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); break; default: - ret = -EINVAL; + break; } if (ret) - return ret; + return 0; return round_rate; } -- 2.7.4