Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751467AbdL3BT2 (ORCPT ); Fri, 29 Dec 2017 20:19:28 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:42285 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750980AbdL3BNU (ORCPT ); Fri, 29 Dec 2017 20:13:20 -0500 X-Google-Smtp-Source: ACJfBotxdzj+MlMG25TCD/NdAjnSi23FskSx5OV0ppvcilerTXC8wOey7OVCYj/HoPsqPglL4ojf2g== From: "Bryan O'Donoghue" To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: pure.logic@nexus-software.ie, Eugeniy Paltsev Subject: [PATCH 07/33] clk: axs10x: change i2s_pll_round_rate return logic Date: Sat, 30 Dec 2017 01:12:46 +0000 Message-Id: <1514596392-22270-8-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> References: <1514596392-22270-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1344 Lines: 41 This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Eugeniy Paltsev Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/axs10x/i2s_pll_clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c index 061260c..20f7ebf 100644 --- a/drivers/clk/axs10x/i2s_pll_clock.c +++ b/drivers/clk/axs10x/i2s_pll_clock.c @@ -119,14 +119,14 @@ static unsigned long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate, if (!pll_cfg) { dev_err(clk->dev, "invalid parent rate=%ld\n", *prate); - return -EINVAL; + return 0; } for (i = 0; pll_cfg[i].rate != 0; i++) if (pll_cfg[i].rate == rate) return rate; - return -EINVAL; + return 0; } static int i2s_pll_set_rate(struct clk_hw *hw, unsigned long rate, -- 2.7.4