Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752791AbeAATJk (ORCPT + 1 other); Mon, 1 Jan 2018 14:09:40 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:33087 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752564AbeAATII (ORCPT ); Mon, 1 Jan 2018 14:08:08 -0500 X-Google-Smtp-Source: ACJfBosH78YV9FyKRXdhfGSjR2W8gpSJz3nAFK2NHvXVAzspOi63wcMgHVdOQMJGL2XBOV2cQuVYZg== From: Bryan O'Donoghue To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Bryan O'Donoghue Subject: [PATCH v2 03/34] clk: composite: allow round_rate to scale past LONG_MAX on 32 bit systems Date: Mon, 1 Jan 2018 19:07:30 +0000 Message-Id: <1514833681-30737-4-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514833681-30737-1-git-send-email-pure.logic@nexus-software.ie> References: <1514833681-30737-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Defining the return value of round_rate as a long and returning error codes as well as the rounded-clock value in the return value of a clk_ops->round_rate callback means that its not possible to return a clock greater than LONG_MAX Hz on a 32 bit system. This patch changes the handling of the return value from round_rate() such that zero indicates an unusable clock and non-zero indicates a successfully rounded clock giving us a full range of 1 Hz to ULONG_MAX Hz on 32 bit systems. Implementations of round_rate() must either return a rounded-clock or zero to indicate error. Signed-off-by: Bryan O'Donoghue Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/clk-composite.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index f3707c3..2090b74 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -66,7 +66,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, long tmp_rate, best_rate = 0; unsigned long rate_diff; unsigned long best_rate_diff = ULONG_MAX; - long rate; + unsigned long rate; int i; if (rate_hw && rate_ops && rate_ops->determine_rate) { @@ -83,8 +83,8 @@ static int clk_composite_determine_rate(struct clk_hw *hw, rate = rate_ops->round_rate(rate_hw, req->rate, &req->best_parent_rate); - if (rate < 0) - return rate; + if (!rate) + return -EINVAL; req->rate = rate; return 0; @@ -99,7 +99,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw, tmp_rate = rate_ops->round_rate(rate_hw, req->rate, &parent_rate); - if (tmp_rate < 0) + if (tmp_rate == 0) continue; rate_diff = abs(req->rate - tmp_rate); -- 2.7.4