Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753150AbeAATfN (ORCPT + 1 other); Mon, 1 Jan 2018 14:35:13 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:46590 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753068AbeAATfI (ORCPT ); Mon, 1 Jan 2018 14:35:08 -0500 X-Google-Smtp-Source: ACJfBouxatXEnMACz/ONSY4fHn7J1W4z86QRVULeUkbkhju4/Ev4bV7IGmP82wwz0PvDIiPv5rMSlg== From: Bryan O'Donoghue To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Bryan O'Donoghue , Joachim Eastwood , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 20/34] clk: nxp: change lpc18xx_pll0_round_rate() return logic Date: Mon, 1 Jan 2018 19:34:46 +0000 Message-Id: <1514835300-381-6-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514835300-381-1-git-send-email-pure.logic@nexus-software.ie> References: <1514835300-381-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Michael Turquette Cc: Stephen Boyd Cc: Joachim Eastwood Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/nxp/clk-lpc18xx-cgu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c index e08bad9..396d4f7 100644 --- a/drivers/clk/nxp/clk-lpc18xx-cgu.c +++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c @@ -381,13 +381,13 @@ static unsigned long lpc18xx_pll0_round_rate(struct clk_hw *hw, if (*prate < rate) { pr_warn("%s: pll dividers not supported\n", __func__); - return -EINVAL; + return 0; } m = DIV_ROUND_UP_ULL(*prate, rate * 2); if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) { pr_warn("%s: unable to support rate %lu\n", __func__, rate); - return -EINVAL; + return 0; } return 2 * *prate * m; -- 2.7.4