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To: Manfred Spraul <manfred@colorfullife.com>
Cc: Mark Hemment <markhe@veritas.com>, linux-kernel@vger.kernel.org
Subject: Re: Q: explicit alignment control for the slab allocator
In-Reply-To: <Pine.LNX.4.21.0103011800460.11260-100000@alloc> <3A9EA940.CB82665C@colorfullife.com>
From: Jes Sorensen <jes@linuxcare.com>
Date: 07 Mar 2001 21:02:03 +0100
In-Reply-To: Manfred Spraul's message of "Thu, 01 Mar 2001 20:55:44 +0100"
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>>>>> "Manfred" == Manfred Spraul <manfred@colorfullife.com> writes:

Manfred> Mark Hemment wrote:
>> As no one uses the feature it could well be broken, but is that a
>> reason to change its meaning?

Manfred> Some hardware drivers use HW_CACHEALIGN and assume certain
Manfred> byte alignments, and arm needs 1024 byte aligned blocks.

Isn't that just a reinvention of SMP_CACHE_BYTES? Or are there
actually machines out there where the inbetween CPU cache line size
differs from the between CPU and DMA controller cache line size?

Jes
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