Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754470AbeAATtD (ORCPT + 1 other); Mon, 1 Jan 2018 14:49:03 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:37470 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753889AbeAATnc (ORCPT ); Mon, 1 Jan 2018 14:43:32 -0500 X-Google-Smtp-Source: ACJfBovrWDLyU/00q5bIeQJyUOUKgmgPxl1Hjgal5ADhueCkShDL28kp2LpvtBhpLSOmu5amODxXdA== From: Bryan O'Donoghue To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Bryan O'Donoghue , Marek Vasut , Vladimir Barinov , Alexey Firago Subject: [PATCH v3 15/34] clk: vc5: change vc5_dbl_round_rate() return logic Date: Mon, 1 Jan 2018 19:42:54 +0000 Message-Id: <1514835793-1104-16-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> References: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Marek Vasut Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Vladimir Barinov Cc: Alexey Firago --- drivers/clk/clk-versaclock5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 9432122..733b402 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -294,7 +294,7 @@ static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) return rate; else - return -EINVAL; + return 0; } static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, -- 2.7.4