Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754549AbeAATtW (ORCPT + 1 other); Mon, 1 Jan 2018 14:49:22 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:42948 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753865AbeAATnb (ORCPT ); Mon, 1 Jan 2018 14:43:31 -0500 X-Google-Smtp-Source: ACJfBotJED3XDPJbYFbJ3HvO3RXHL7N/edxRnTAyqZ/Ed8oKY0L4C0w5eG7nQ2to9y0bJokhyJBQKw== From: Bryan O'Donoghue To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Bryan O'Donoghue , Marek Vasut , Vladimir Barinov , Alexey Firago Subject: [PATCH v3 14/34] clk: vc5: change vc5_pfd_round_rate() return logic Date: Mon, 1 Jan 2018 19:42:53 +0000 Message-Id: <1514835793-1104-15-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> References: <1514835793-1104-1-git-send-email-pure.logic@nexus-software.ie> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This patch updates the round_rate() logic here to return zero instead of a negative number on error. In conjunction with higher-level changes associated with acting on the return value of clk_ops->round_rate() it is then possible to have clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of the current limitation of 1 Hz to LONG_MAX Hz. Signed-off-by: Bryan O'Donoghue Cc: Marek Vasut Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Vladimir Barinov Cc: Alexey Firago --- drivers/clk/clk-versaclock5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 7c7b369..9432122 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -351,7 +351,7 @@ static unsigned long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, /* PLL cannot operate with input clock above 50 MHz. */ if (rate > 50000000) - return -EINVAL; + return 0; /* CLKIN within range of PLL input, feed directly to PLL. */ if (*parent_rate <= 50000000) @@ -359,7 +359,7 @@ static unsigned long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, idiv = DIV_ROUND_UP(*parent_rate, rate); if (idiv > 127) - return -EINVAL; + return 0; return *parent_rate / idiv; } -- 2.7.4