Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751365AbeABQnL (ORCPT + 1 other); Tue, 2 Jan 2018 11:43:11 -0500 Received: from mail.kmu-office.ch ([178.209.48.109]:53133 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751100AbeABQm3 (ORCPT ); Tue, 2 Jan 2018 11:42:29 -0500 From: Stefan Agner To: shawnguo@kernel.org, kernel@pengutronix.de Cc: fabio.estevam@nxp.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH 4/7] ARM: dts: imx6ul: add interrupt of virt-capable GIC Date: Tue, 2 Jan 2018 17:42:20 +0100 Message-Id: <20180102164223.15230-4-stefan@agner.ch> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180102164223.15230-1-stefan@agner.ch> References: <20180102164223.15230-1-stefan@agner.ch> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The Cortex-A7 and its GIC support virtualization extensions. To make use of them the CPU private interrupt needs to be specified. Signed-off-by: Stefan Agner --- arch/arm/boot/dts/imx6ul.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 1b14e4d39c26..993fbdbdd506 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -100,8 +100,10 @@ intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x00a01000 0x1000>, <0x00a02000 0x2000>, <0x00a04000 0x2000>, -- 2.15.1