Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752654AbeADJlV (ORCPT + 1 other); Thu, 4 Jan 2018 04:41:21 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:53223 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752616AbeADJlS (ORCPT ); Thu, 4 Jan 2018 04:41:18 -0500 X-UUID: cbeaf3bfb7a74890ba788c6765099a66-20180104 From: To: , , , , CC: , , Ryder Lee , Sean Wang Subject: [PATCH 12/12] arm64: dts: mt7622: add SATA device nodes Date: Thu, 4 Jan 2018 17:41:02 +0800 Message-ID: <0916715ee16930ca08d9a70903faa959df802b3d.1515057696.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Ryder Lee This patch adds SATA support fot MT7622. Signed-off-by: Ryder Lee Signed-off-by: Sean Wang --- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 53d4efd..cafb860 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -325,6 +325,14 @@ status = "okay"; }; +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spic0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 2801b7d..f875f10 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -545,6 +546,45 @@ }; }; + sata: sata@1a200000 { + compatible = "mediatek,mt7622-ahci", + "mediatek,mtk-ahci"; + reg = <0 0x1a200000 0 0x1100>; + interrupts = ; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + status = "disabled"; + }; + + sata_phy: sata-phy@1a243000 { + compatible = "mediatek,generic-tphy-v1"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + sata_port: sata-phy@1a243000 { + reg = <0 0x1a243000 0 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; -- 2.7.4