Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752695AbeADJm7 (ORCPT + 1 other); Thu, 4 Jan 2018 04:42:59 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:53223 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752546AbeADJlN (ORCPT ); Thu, 4 Jan 2018 04:41:13 -0500 X-UUID: 8d8d6151e4ab4c6a8348f0782e436194-20180104 From: To: , , , , CC: , , Sean Wang Subject: [PATCH 07/12] arm64: dts: mt7622: turn uart0 clock to real ones Date: Thu, 4 Jan 2018 17:40:57 +0800 Message-ID: <0fc5e7b4b75a781649c189e91c6e270d0d82d1ea.1515057696.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Sean Wang This patch also cleans up two oscillators that provide clocks for MT7623. Switch the uart clocks to the real ones while at it. Signed-off-by: Sean Wang Cc: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 90b2761..3b6f082 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -88,18 +88,6 @@ }; }; - uart_clk: dummy25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - bus_clk: dummy280m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <280000000>; - }; - pwrap_clk: dummy40m { compatible = "fixed-clock"; clock-frequency = <40000000>; @@ -231,7 +219,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>, <&bus_clk>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; clock-names = "baud", "bus"; status = "disabled"; }; -- 2.7.4