Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752699AbeADJn1 (ORCPT + 1 other); Thu, 4 Jan 2018 04:43:27 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:64481 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752544AbeADJlN (ORCPT ); Thu, 4 Jan 2018 04:41:13 -0500 X-UUID: 7be05707bdaa4cc0b1c6cde423ca7239-20180104 From: To: , , , , CC: , , Sean Wang , Viresh Kumar Subject: [PATCH 06/12] arm64: dts: mt7622: add cpufreq related device nodes Date: Thu, 4 Jan 2018 17:40:56 +0800 Message-ID: <7e61305594b7bbcdefe31f64ca5603cbdbd9f4cf.1515057696.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Sean Wang Add clocks, regulators and opp information into cpu nodes. In addition, the power supply for cpu nodes is deployed on mt7622-rfb1 board. Signed-off-by: Sean Wang Cc: Viresh Kumar --- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 49 ++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index f72f1f5..4762168 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -20,6 +20,18 @@ bootargs = "console=ttyS0,115200n1"; }; + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + gpio_keys { compatible = "gpio-keys-polled"; poll-interval = <100>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 5b7f0a3..90b2761 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -18,6 +18,50 @@ #address-cells = <2>; #size-cells = <2>; + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp-300000000 { + opp-hz = /bits/ 64 <30000000>; + opp-microvolt = <950000>; + }; + + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000>; + }; + + opp-812500000 { + opp-hz = /bits/ 64 <812500000>; + opp-microvolt = <1100000>; + }; + + opp-1025000000 { + opp-hz = /bits/ 64 <1025000000>; + opp-microvolt = <1150000>; + }; + + opp-1137500000 { + opp-hz = /bits/ 64 <1137500000>; + opp-microvolt = <1200000>; + }; + + opp-1262500000 { + opp-hz = /bits/ 64 <1262500000>; + opp-microvolt = <1250000>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1310000>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -26,6 +70,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; clock-frequency = <1300000000>; }; @@ -34,6 +82,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; clock-frequency = <1300000000>; }; -- 2.7.4