Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751376AbeAEAIg (ORCPT + 1 other); Thu, 4 Jan 2018 19:08:36 -0500 Received: from mga06.intel.com ([134.134.136.31]:28178 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751108AbeAEAIf (ORCPT ); Thu, 4 Jan 2018 19:08:35 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,316,1511856000"; d="scan'208";a="24442900" Subject: Re: [PATCH 3/7] x86/enter: Use IBRS on syscall and interrupts To: Peter Zijlstra , Tim Chen References: <0c525c4c6c817e9c42c7ed583d86dc591a86efde.1515086770.git.tim.c.chen@linux.intel.com> <20180104223321.GD32035@hirez.programming.kicks-ass.net> Cc: Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Greg KH , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , linux-kernel@vger.kernel.org From: Dave Hansen Message-ID: <8e382c5a-1d8d-44e6-87f4-176305493a47@intel.com> Date: Thu, 4 Jan 2018 16:08:33 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180104223321.GD32035@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 01/04/2018 02:33 PM, Peter Zijlstra wrote: > On Thu, Jan 04, 2018 at 09:56:44AM -0800, Tim Chen wrote: >> Set IBRS upon kernel entrance via syscall and interrupts. Clear it >> upon exit. > > So not only did we add a CR3 write, we're now adding an MSR write to the > entry/exit paths. Please tell me that these are 'fast' MSRs? Given > people are already reporting stupid numbers with just the existing > PTI/CR3, what kind of pain are we going to get from adding this? This "dynamic IBRS" that does runtime switching will not be on by default and will be patched around by alternatives unless someone explicitly opts in. If you decide you want the additional protection that it provides, you can take the performance hit. How much is that? We've been saying that these new MSRs are roughly as expensive as the CR3 writes. How expensive are those? Don't take my word for it, a few folks were talking about it today: Google says[1]: "We see negligible impact on performance." Amazon says[2]: "We don’t expect meaningful performance impact." I chopped a few qualifiers out of there, but I think that roughly captures the sentiment. 1. https://security.googleblog.com/2018/01/more-details-about-mitigations-for-cpu_4.html 2. http://www.businessinsider.com/google-amazon-performance-hit-meltdown-spectre-fixes-overblown-2018-1