Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751580AbeAEKbx (ORCPT + 1 other); Fri, 5 Jan 2018 05:31:53 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:51646 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbeAEKbu (ORCPT ); Fri, 5 Jan 2018 05:31:50 -0500 From: Matt Redfearn To: Ralf Baechle , Thomas Gleixner CC: , Matt Redfearn , "Jason Cooper" , Dengcheng Zhu , , Philippe Ombredanne , Paul Burton , Kate Stewart , Greg Kroah-Hartman , Marc Zyngier Subject: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Date: Fri, 5 Jan 2018 10:31:04 +0000 Message-ID: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] X-BESS-ID: 1515148289-298553-16961-111618-10 X-BESS-VER: 2017.16-r1712230000 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188674 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This series enables the MIPS GIC driver to make use of the EIC mode supported in some MIPS cores. In this mode, the cores 6 interrupt lines are switched to represent a vector number, 0..63. Currently all GIC interrupts are routed to a single CPU interrupt pin, but this is inefficient since we end up checking both local and shared interrupt flag registers for both local and shared interrupts. This introduces additional latency into the interrupt paths. With EIC mode this can be improved by using separate vectors for local and shared interrupts. This series is based on 4.15-rc6 and has been tested on Boston, Malta & SEAD3 MIPS platforms implementing a GIC with and without EIC mode supported in hardware. Matt Redfearn (6): MIPS: Move ehb() to barrier.h MIPS: CPS: Introduce mips_gic_enable_eic MIPS: Generic: Support GIC in EIC mode irqchip/mips-gic: Always attempt to enable EIC mode irqchip/mips-gic: Use separate vector for shared interrupts in EIC mode irqchip/mips-gic: Separate local interrupt handling. arch/mips/generic/irq.c | 18 +++++++++--------- arch/mips/include/asm/barrier.h | 13 +++++++++++++ arch/mips/include/asm/mips-gic.h | 22 ++++++++++++++++++++++ arch/mips/include/asm/mipsmtregs.h | 8 -------- drivers/irqchip/irq-mips-gic.c | 34 +++++++++++++++++++++++----------- 5 files changed, 67 insertions(+), 28 deletions(-) -- 2.7.4