Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751637AbeAEKcR (ORCPT + 1 other); Fri, 5 Jan 2018 05:32:17 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:48061 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751560AbeAEKcP (ORCPT ); Fri, 5 Jan 2018 05:32:15 -0500 From: Matt Redfearn To: Ralf Baechle , Thomas Gleixner CC: , Matt Redfearn , Dengcheng Zhu , , Paul Burton , Marc Zyngier Subject: [PATCH 2/6] MIPS: CPS: Introduce mips_gic_enable_eic Date: Fri, 5 Jan 2018 10:31:06 +0000 Message-ID: <1515148270-9391-3-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] X-BESS-ID: 1515148323-637137-12098-550431-1 X-BESS-VER: 2017.16-r1712230000 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188674 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The MIPS GIC supports running in External Interrupt Controller (EIC) mode, in which the GIC can raise up to 64 separate interrupts rather than the usual 6. This mode is enabled by setting bit GIC_VL_CTL.EIC. If the bit sticks, then EIC mode is present and becomes enabled. Otherwise this bit is read-only 0 and setting it will have no effect. The CP0 register Config3 bit VEIC indicates the status of EIC mode, and effectively reflects GIC_VL_CTL.EIC. After attempting to enable EIC mode, read back Config3.VEIC to determine if VEIC mode is present and has been activated. If so, update the boot CPU flags to reflect that VEIC mode is now active. Signed-off-by: Matt Redfearn --- arch/mips/include/asm/mips-gic.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 558059a8f218..b8345b117224 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -314,6 +314,28 @@ static inline bool mips_gic_present(void) return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base; } + +/** + * mips_gic_enable_eic() - Enable EIC mode if supported + * + * Attempt to enable the GICs EIC mode if supported by the hardware. + * EIC is enabled via the GIC CTL register. If the bit sticks, then the mode + * is supported and active. CP0.Config3.VEIC reflects this state and is read + * to determine if the mode has successfully been activated. If it has, update + * the boot cpu flags such that cpu_has_veic reflects the new mode. + */ +static inline void mips_gic_enable_eic(void) +{ + set_gic_vl_ctl(GIC_VX_CTL_EIC); + mb(); /* Ensure write to GIC register completes */ + ehb(); /* Ensure mfc0 does not start early */ + if (read_c0_config3() & MIPS_CONF3_VEIC) { + /* GIC & CPU now in VEIC mode */ + pr_debug("GIC EIC mode activated\n"); + boot_cpu_data.options |= MIPS_CPU_VEIC; + } +} + /** * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq * -- 2.7.4