Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751797AbeAEKd5 (ORCPT + 1 other); Fri, 5 Jan 2018 05:33:57 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.150.225]:44376 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751092AbeAEKdw (ORCPT ); Fri, 5 Jan 2018 05:33:52 -0500 From: Matt Redfearn To: Ralf Baechle , Thomas Gleixner CC: , Matt Redfearn , "Marc Zyngier" , Jason Cooper , Subject: [PATCH 4/6] irqchip/mips-gic: Always attempt to enable EIC mode Date: Fri, 5 Jan 2018 10:31:08 +0000 Message-ID: <1515148270-9391-5-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] X-BESS-ID: 1515148415-298554-4845-324352-2 X-BESS-VER: 2017.16-r1712230000 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188674 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The MIPS GIC supports running in External Interrupt Controller (EIC) mode, in which the GIC can raise up to 64 separate interrupts rather than the usual 6. This mode is enabled by setting bit GIC_VL_CTL.EIC. If the bit sticks, then EIC mode is present and becomes enabled. Otherwise this bit is read-only 0 and setting it will have no effect. The CP0 register Config3 bit VEIC indicates the status of EIC mode, and effectively reflects GIC_VL_CTL.EIC. After attempting to enable EIC mode, read back Config3.VEIC to determine if VEIC mode is present and has been activated. If so, update the boot CPU flags to reflect that VEIC mode is now active. Signed-off-by: Matt Redfearn --- drivers/irqchip/irq-mips-gic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ef92a4d2038e..ee391f42e97d 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -725,6 +725,9 @@ static int __init gic_of_init(struct device_node *node, gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS); gic_shared_intrs = (gic_shared_intrs + 1) * 8; + /* Enable EIC mode if supported. */ + mips_gic_enable_eic(); + if (cpu_has_veic) { /* Always use vector 1 in EIC mode */ gic_cpu_pin = 0; -- 2.7.4