Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752012AbeAEO0e (ORCPT + 1 other); Fri, 5 Jan 2018 09:26:34 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:43342 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751982AbeAEO0c (ORCPT ); Fri, 5 Jan 2018 09:26:32 -0500 X-Google-Smtp-Source: ACJfBos5sPOJUKx1cq0gyTA7ihlbTBFVRGRHw5iiP20JSP5iDT6sj5D23rIMCOv2Jgh71Ea2rdOGMA== Subject: Re: [PATCH 0/7] IBRS patch series To: Greg KH , Yves-Alexis Perez Cc: Henrique de Moraes Holschuh , Tim Chen , Justin Forbes , Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , linux-kernel@vger.kernel.org References: <2c1e7299-56ea-07ec-8077-471f17ad3c79@linux.intel.com> <1515099712.30693.22.camel@debian.org> <20180105132856.GA12036@kroah.com> <1515160065.3305.6.camel@debian.org> <20180105140145.GA24434@kroah.com> From: Paolo Bonzini Message-ID: <2b40f988-e773-97a5-77ca-de0908887ae2@redhat.com> Date: Fri, 5 Jan 2018 15:26:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180105140145.GA24434@kroah.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 05/01/2018 15:01, Greg KH wrote: >> Obviously it lacks a *lot* of processors (especially pre-Haswell). > > I'm running Arch, but it would be nice to know where those microcode > updates came from, given that they aren't on the "official" Intel page > yet :) Those from November seem way too early to include IBRS/IBPB. Maybe the two from December 3rd, but I wouldn't be 100% sure. So it would be even nicer to know how those microcode updates were tested. (And by the way, the LFENCE change is for variant 1 aka CVE-2017-5753). Paolo