Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752175AbeAEQH5 (ORCPT + 1 other); Fri, 5 Jan 2018 11:07:57 -0500 Received: from mail-bl2nam02on0064.outbound.protection.outlook.com ([104.47.38.64]:3660 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751784AbeAEQHy (ORCPT ); Fri, 5 Jan 2018 11:07:54 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; From: Tom Lendacky Subject: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Peter Zijlstra , Linus Torvalds , Dave Hansen , Borislav Petkov , Thomas Gleixner , Tim Chen , Greg Kroah-Hartman , David Woodhouse , Paul Turner Date: Fri, 05 Jan 2018 10:07:46 -0600 Message-ID: <20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net> In-Reply-To: <20180105160736.23786.45026.stgit@tlendack-t1.amdoffice.net> References: <20180105160736.23786.45026.stgit@tlendack-t1.amdoffice.net> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; 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This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serializing. Signed-off-by: Tom Lendacky --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ab02261..1e7d710 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -352,6 +352,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcb75dc..fbd439e 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { + /* + * Use LFENCE for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + /* MFENCE stops RDTSC speculation */ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); }