Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752362AbeAERHF (ORCPT + 1 other); Fri, 5 Jan 2018 12:07:05 -0500 Received: from mga05.intel.com ([192.55.52.43]:6230 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752209AbeAERHE (ORCPT ); Fri, 5 Jan 2018 12:07:04 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,319,1511856000"; d="scan'208";a="18532956" Subject: Re: [PATCH 1/7] x86/feature: Detect the x86 feature to control Speculation To: Tom Lendacky , David Woodhouse , Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Greg KH Cc: Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , linux-kernel@vger.kernel.org References: <427aa76dea14532dea7e49f0bce4e7cf1dea7c6f.1515086770.git.tim.c.chen@linux.intel.com> <1515150882.29312.114.camel@infradead.org> <197c55e4-4341-8151-6463-d2a91f0cc95b@amd.com> From: Tim Chen Message-ID: Date: Fri, 5 Jan 2018 09:07:02 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: <197c55e4-4341-8151-6463-d2a91f0cc95b@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 01/05/2018 07:14 AM, Tom Lendacky wrote: > On 1/5/2018 5:14 AM, David Woodhouse wrote: >> On Thu, 2018-01-04 at 09:56 -0800, Tim Chen wrote: >>> cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature >>> IA32_SPEC_CTRL (0x48) and IA32_PRED_CMD (0x49) >>> IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS) >>> IA32_PRED_CMD, bit0 – Indirect Branch Prediction Barrier (IBPB) >> >> In a previous iteration of these patches, hadn't you already merged >> support for the AMD variant? Where'd that go? > > It looks like this series is strictly IBRS related. Even though some of > the IBPB definitions are in here, there isn't support later for indicating > IBPB is in use or any places where IBPB would be used. I was assuming that > there would be another series for IBPB support. Is that the plan? IBPB is meant to be a separate series. We want to get retpoline and IBRS out first. > > AMD is covered by the IBRS support as is, but we also have support for > the IBPB feature alone, identified by a different CPUID bit. I was > waiting for the IBPB series to see if I needed to submit anything or > whether the patches were included. > Tim