Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752518AbeAESZ1 (ORCPT + 1 other); Fri, 5 Jan 2018 13:25:27 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:56020 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752342AbeAESZY (ORCPT ); Fri, 5 Jan 2018 13:25:24 -0500 From: Paul Cercueil To: Ralf Baechle Cc: Maarten ter Huurne , Paul Burton , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Paul Cercueil Subject: [PATCH v6 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Date: Fri, 5 Jan 2018 19:25:00 +0100 Message-Id: <20180105182513.16248-3-paul@crapouillou.net> In-Reply-To: <20180105182513.16248-1-paul@crapouillou.net> References: <20180102150848.11314-1-paul@crapouillou.net> <20180105182513.16248-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil Acked-by: Stephen Boyd --- drivers/clk/ingenic/cgu.c | 2 ++ 1 file changed, 2 insertions(+) v2: No changes v3: No changes v4: No changes v5: No changes v6: No changes diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index ab393637f7b0..a2e73a6d60fd 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) div *= clk_info->div.div; rate /= div; + } else if (clk_info->type & CGU_CLK_FIXDIV) { + rate /= clk_info->fixdiv.div; } return rate; -- 2.11.0