Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753769AbeAFVLK (ORCPT + 1 other); Sat, 6 Jan 2018 16:11:10 -0500 Received: from terminus.zytor.com ([65.50.211.136]:43775 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753390AbeAFVLI (ORCPT ); Sat, 6 Jan 2018 16:11:08 -0500 Date: Sat, 6 Jan 2018 13:05:35 -0800 From: tip-bot for Tom Lendacky Message-ID: Cc: thomas.lendacky@amd.com, pjt@google.com, mingo@kernel.org, bp@alien8.de, torvalds@linux-foundation.org, peterz@infradead.org, gregkh@linux-foundation.org, linux-kernel@vger.kernel.org, hpa@zytor.com, dave.hansen@intel.com, dwmw@amazon.co.uk, tim.c.chen@linux.intel.com, tglx@linutronix.de Reply-To: linux-kernel@vger.kernel.org, dave.hansen@intel.com, hpa@zytor.com, gregkh@linux-foundation.org, pjt@google.com, thomas.lendacky@amd.com, torvalds@linux-foundation.org, peterz@infradead.org, bp@alien8.de, mingo@kernel.org, dwmw@amazon.co.uk, tglx@linutronix.de, tim.c.chen@linux.intel.com In-Reply-To: <20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net> References: <20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/cpu/AMD: Make LFENCE a serializing instruction Git-Commit-ID: 0592b0bce1694957fed178fc52f4b11576714b07 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Commit-ID: 0592b0bce1694957fed178fc52f4b11576714b07 Gitweb: https://git.kernel.org/tip/0592b0bce1694957fed178fc52f4b11576714b07 Author: Tom Lendacky AuthorDate: Fri, 5 Jan 2018 10:07:46 -0600 Committer: Thomas Gleixner CommitDate: Sat, 6 Jan 2018 21:57:40 +0100 x86/cpu/AMD: Make LFENCE a serializing instruction To aid in speculation control, make LFENCE a serializing instruction. This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serializing. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Peter Zijlstra Cc: Linus Torvalds Cc: Dave Hansen Cc: Tim Chen Cc: Greg Kroah-Hartman Cc: David Woodhouse Cc: Paul Turner Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20180105160746.23786.11850.stgit@tlendack-t1.amdoffice.net --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ab02261..1e7d710 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -352,6 +352,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcb75dc..fbd439e 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { + /* + * Use LFENCE for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + /* MFENCE stops RDTSC speculation */ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); }