Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754212AbeAGRMY (ORCPT + 1 other); Sun, 7 Jan 2018 12:12:24 -0500 Received: from mga03.intel.com ([134.134.136.65]:1082 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754074AbeAGRMW (ORCPT ); Sun, 7 Jan 2018 12:12:22 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,326,1511856000"; d="scan'208";a="18192968" Subject: Re: [PATCH v2 2/8] x86/enter: MACROS to set/clear IBRS To: Borislav Petkov Cc: Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Greg KH , Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , David Woodhouse , linux-kernel@vger.kernel.org References: <20180107120303.dbrngl7gjmxns7k6@pd.tnic> From: Tim Chen Message-ID: <08550e2c-1a7c-78bd-2b95-ed3dad8f7dc8@linux.intel.com> Date: Sun, 7 Jan 2018 09:12:21 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20180107120303.dbrngl7gjmxns7k6@pd.tnic> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 01/07/2018 04:03 AM, Borislav Petkov wrote: > On Fri, Jan 05, 2018 at 06:12:17PM -0800, Tim Chen wrote: > >> Subject: Re: [PATCH v2 2/8] x86/enter: MACROS to set/clear IBRS > > Your subject needs to have a verb and not scream: > > Subject: [PATCH v2 2/8] x86/entry: Add macros to set/clear IBRS > >> Create macros to control IBRS. Use these macros to enable IBRS on kernel entry >> paths and disable IBRS on kernel exit paths. >> >> The registers rax, rcx and rdx are touched when controlling IBRS >> so they need to be saved when they can't be clobbered. >> >> Signed-off-by: Tim Chen >> --- >> arch/x86/entry/calling.h | 74 ++++++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> >> diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h >> index 45a63e0..09c870d 100644 >> --- a/arch/x86/entry/calling.h >> +++ b/arch/x86/entry/calling.h >> @@ -6,6 +6,8 @@ >> #include >> #include >> #include >> +#include >> +#include >> >> /* >> >> @@ -347,3 +349,75 @@ For 32-bit we have the following conventions - kernel is built with >> .Lafter_call_\@: >> #endif >> .endm >> + >> +/* >> + * IBRS related macros >> + */ >> +.macro PUSH_MSR_REGS >> + pushq %rax >> + pushq %rcx >> + pushq %rdx >> +.endm >> + >> +.macro POP_MSR_REGS >> + popq %rdx >> + popq %rcx >> + popq %rax >> +.endm >> + >> +.macro WRMSR_ASM msr_nr:req eax_val:req > > WRMSR as a name is good enough. > > Also, you need edx_val:req too in case we decide to reuse that macro > for something else later. Which I'm pretty sure we will, once it is out > there. > >> + movl \msr_nr, %ecx >> + movl $0, %edx > > ... and then > > movl \edx_val, %edx > >> + movl \eax_val, %eax >> +.endm >> + >> +.macro ENABLE_IBRS >> + ALTERNATIVE "jmp .Lskip_\@", "", X86_FEATURE_SPEC_CTRL >> + PUSH_MSR_REGS >> + WRMSR_ASM $MSR_IA32_SPEC_CTRL, $SPEC_CTRL_FEATURE_ENABLE_IBRS > > This is overwriting the previous contents of the MSR. You need to read > it and OR-in its bits [63:2] with SPEC_CTRL_FEATURE_ENABLE_IBRS and > clear bit 0. > > Unless the rest of this MSR is not going to be used for anything else. > Then you're fine. > Currently we are not using other bits. When the time comes that we have other bits in this MSR used, we will change this. Tim