Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755298AbeAHCWe (ORCPT + 1 other); Sun, 7 Jan 2018 21:22:34 -0500 Received: from mail-bn3nam01on0070.outbound.protection.outlook.com ([104.47.33.70]:62239 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754961AbeAHCWQ (ORCPT ); Sun, 7 Jan 2018 21:22:16 -0500 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=fail action=none header.from=nxp.com; From: Anson Huang To: , , , , , , , CC: , , , Subject: [PATCH V3 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul Date: Mon, 8 Jan 2018 10:04:51 +0800 Message-ID: <1515377091-10422-2-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515377091-10422-1-git-send-email-Anson.Huang@nxp.com> References: <1515377091-10422-1-git-send-email-Anson.Huang@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131598517048283001;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(39380400002)(346002)(39860400002)(376002)(396003)(2980300002)(1109001)(1110001)(339900001)(199004)(189003)(77096006)(305945005)(72206003)(16586007)(110136005)(498600001)(4326008)(68736007)(316002)(81166006)(356003)(8936002)(50226002)(59450400001)(86362001)(104016004)(36756003)(7416002)(106466001)(81156014)(105606002)(8676002)(47776003)(6666003)(2201001)(5660300001)(2906002)(54906003)(8656006)(53936002)(2950100002)(97736004)(76176011)(85426001)(50466002)(48376002)(51416003)(32563001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR03MB2354;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; 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clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); + if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { + clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); + clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); + } } else { clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); @@ -260,6 +264,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev) of_node_put(np); } +#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 + +static void imx6ul_opp_check_speed_grading(struct device *dev) +{ + struct device_node *np; + void __iomem *base; + u32 val; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); + if (!np) + return; + + base = of_iomap(np, 0); + if (!base) { + dev_err(dev, "failed to map ocotp\n"); + goto put_node; + } + + /* + * Speed GRADING[1:0] defines the max speed of ARM: + * 2b'00: Reserved; + * 2b'01: 528000000Hz; + * 2b'10: 696000000Hz; + * 2b'11: Reserved; + * We need to set the max speed of ARM according to fuse map. + */ + val = readl_relaxed(base + OCOTP_CFG3); + val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 0x3; + if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) + if (dev_pm_opp_disable(dev, 696000000)) + dev_warn(dev, "failed to disable 696MHz OPP\n"); + iounmap(base); +put_node: + of_node_put(np); +} + static int imx6q_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; @@ -314,7 +355,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto put_reg; } - imx6q_opp_check_speed_grading(cpu_dev); + if (of_machine_is_compatible("fsl,imx6ul")) + imx6ul_opp_check_speed_grading(cpu_dev); + else + imx6q_opp_check_speed_grading(cpu_dev); /* Because we have added the OPPs here, we must free them */ free_opp = true; -- 1.9.1