Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755845AbeAHGyo (ORCPT + 1 other); Mon, 8 Jan 2018 01:54:44 -0500 Received: from mail-by2nam03on0078.outbound.protection.outlook.com ([104.47.42.78]:59712 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755827AbeAHGym (ORCPT ); Mon, 8 Jan 2018 01:54:42 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jayachandran.Nair@cavium.com; From: Jayachandran C To: Will Deacon , marc.zyngier@arm.com Cc: linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org, Jayachandran C Subject: [PATCH 1/2] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Sun, 7 Jan 2018 22:53:35 -0800 Message-Id: <1515394416-166994-1-git-send-email-jnair@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <20180108063115.GA163286@jc-sabre> References: <20180108063115.GA163286@jc-sabre> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: MWHPR1701CA0016.namprd17.prod.outlook.com (2603:10b6:301:14::26) To DM2PR0701MB1066.namprd07.prod.outlook.com (2a01:111:e400:2472::19) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5317d109-b1db-4b50-f88b-08d55664b01d X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(5600026)(4604075)(2017052603307)(7153060)(7193020);SRVR:DM2PR0701MB1066; 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Signed-off-by: Jayachandran C --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 84385b9..cce5735 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -89,6 +89,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -102,6 +103,8 @@ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #ifndef __ASSEMBLY__ -- 2.7.4